Author: Nurul Mastura RoslanPublisher:
ISBN:
Category :
Languages : en
Pages : 112
Book Description
The Study of Negative Bias Temperature Instability (NBTI) Degradation and Its Impact for Digital Circuit Reliability
Author: Nurul Mastura RoslanPublisher:
ISBN:
Category :
Languages : en
Pages : 112
Book Description
Bias Temperature Instability for Devices and Circuits
Author: Tibor GrasserPublisher: Springer Science & Business Media
ISBN: 1461479096
Category : Technology & Engineering
Languages : en
Pages : 805
Book Description
This book provides a single-source reference to one of the more challenging reliability issues plaguing modern semiconductor technologies, negative bias temperature instability. Readers will benefit from state-of-the art coverage of research in topics such as time dependent defect spectroscopy, anomalous defect behavior, stochastic modeling with additional metastable states, multiphonon theory, compact modeling with RC ladders and implications on device reliability and lifetime.
Design of Negative Bias Temperature Instability (NBTI) Tolerant Register File
Author: Saurabh Eknath KothawadePublisher:
ISBN:
Category :
Languages : en
Pages : 58
Book Description
PUBLIC ABSTRACT: Negative Bias Temperature Instability (NBTI) is becoming a major reliability problem in the semiconductor industry. As time passes, NBTI reduces the capacity of performing correct computations in the microprocessor. Hence, after certain time period, the microprocessor may fail to work as we expect, causing failure of the entire system it is part of. In this research, we study the root cause of the failure due to NBTI effect. Based on our findings, we propose multiple methods to reduce the negative impact of NBTI on a microprocessor. We build a comprehensive experimental setup to consider real world effects in a microprocessor. We evaluate our methods against the previous work and find that our methods substantially improve the processor reliability. This research could be useful in the future to extend lifetime of the processor.
Negative Bias Temperature Instability and Charge Trapping Effects on Analog and Digital Circuit Reliability
Author: Yixin YuPublisher:
ISBN:
Category :
Languages : en
Pages : 63
Book Description
Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at midfrequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.
A Study on Negative Bias Temperature Instability on Digital Circuits
Author: Xiangning YangPublisher:
ISBN:
Category :
Languages : en
Pages : 32
Book Description
New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits
Author: Sudheer PadalaPublisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 64
Book Description
Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation and results are discussed. This thesis focuses on developing a model for simulating impact of NBTI effects at circuit level. The model mimics the effects of degradation caused by the defects. The NBTI model developed in this work is validated and sanity checked by using the simulation data from silvaco and gives excellent results. Furthermore the susceptibility of CMOS circuits such as the CMOS inverter, and a ring oscillator to NBTI is investigated. The results show that the oscillation frequency of a ring oscillator decreases and the SET pulse broadens with the NBTI.
Negative Bias Temperature Instability (NBTI) Experiment
Author: Publisher:
ISBN:
Category : Reliability
Languages : en
Pages : 57
Book Description
The phenomenon known as Negative Bias Temperature Instability (NBTI) impacts the operational characteristics of Complementary Metal Oxide Semiconductor (CMOS) devices, and tends to have a stronger effect on p-channel devices. This instability is observed with an applied "on" biasing during normal operation and can be accelerated with thermal stress. A normal applied electrical bias on CMOS transistors can lead to the generation of interface states at the junction of the gate oxide and the transistor channel. The hydrogen that normally passivates the interface states can diffuse away from the interface. As a result, the threshold voltage and transconductance will change. These interface states can be measured to determine the susceptibility to NBTI of the devices. For this purpose, a charge pumping experiment and other On-the-Fly techniques at certain temperatures can provide the interface state density and other valuable data. NBTI can impact current technological fabrication processes, such as those provided to the government from IBM. This paper explains this testing of current submicron transistor technology that will be used for military applications.
Modeling and Simulation of Negative Bias Temperature Instability
Author: Robert EntnerPublisher:
ISBN: 9783836459976
Category : Field-effect transistors
Languages : en
Pages : 126
Book Description
Semiconductor process and device simulators are well established tools for the reduction of the development time for semiconductor devices. Nowadays simulation efforts go beyond solving the basic semiconductor device equations. Especially the modeling and simulation of aging processes has tremendously gained in importance. This book gives insight into the topic of semiconductor device simulation and focuses on the modeling of degradation mechanisms. Negative bias temperature instability (NBTI) causes degradation of MOS structures at elevated temperatures and negative gate voltages. An elaborate investigation of literature from the first report to the recent understanding of this degradation mechanism is presented. A comprehensive model is derived, combining research results from different groups and the coupling to the basic semiconductor device equations. The new NBTI model is compared to measurement data and gives excellent results. This book is addressed to researchers in the field of semiconductor process development but also recommended to engineers in IC design to strengthen their understanding for device degradation.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Author: Nadine AzemardPublisher: Springer Science & Business Media
ISBN: 354074441X
Category : Computers
Languages : en
Pages : 595
Book Description
This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Low-Power Variation-Tolerant Design in Nanometer Silicon
Author: Swarup BhuniaPublisher: Springer Science & Business Media
ISBN: 1441974180
Category : Technology & Engineering
Languages : en
Pages : 444
Book Description
Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
