Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits PDF full book. Access full book title Parametric Macro-modeling for Design-for-reliability of Hot-carrier Resistant MOS VLSI Circuits by Weishi Sun. Download full books in PDF and EPUB format.
Author: Weishi Sun
Publisher:
ISBN:
Category :
Languages : en
Pages : 142
Get Book Here
Book Description
Author: Weishi Sun
Publisher:
ISBN:
Category :
Languages : en
Pages : 142
Get Book Here
Book Description
Author: Yusuf Leblebici
Publisher: Springer Science & Business Media
ISBN: 1461532507
Category : Technology & Engineering
Languages : en
Pages : 223
Get Book Here
Book Description
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 82
Get Book Here
Book Description
This report describes the development and application of parametric and geometry based macro-models of hot-carrier induced dynamic degradation in MOS VLSI circuits. Previously, a simulation based approach has been used for reliability analysis, but this is inefficient for reliability assessment of very large scale integrated circuits. Geometry-based macro-models for hot-carrier reliability estimation have been developed. The macro-models express hot-carrier damage as functions of designable parameters such as transistor size (W), output loading capacitance (C1) and the input signal slew rate (a). A prototype rule- based reliability diagnosis tool, iRULE, has been developed. This tool uses the macro-models for designing hot-carrier resistant circuits without the need for transient reliability simulations. This provides the ability to analyze very large circuits with more than one million transistors on a workstation in a short amount of time. This report also describes a fast timing reliability simulation tool, ILLIADS-R, that can accurately estimate hot-carrier degradation while providing several orders of magnitude speed up over traditional transistor-level circuit simulators. Reliability, Hot-carrier degradation, VLSI CMOS Circuits, Simulation.
Author: Cheng Wang
Publisher: Springer Science & Business Media
ISBN: 1468485474
Category : Science
Languages : en
Pages : 345
Get Book Here
Book Description
As device dimensions decrease, hot-carrier effects, which are due mainly to the presence of a high electric field inside the device, are becoming a major design concern. On the one hand, the detrimental effects-such as transconductance degradation and threshold shift-need to be minimized or, if possible, avoided altogether. On the other hand, performance such as the programming efficiency of nonvolatile memories or the carrier velocity inside the devices-need to be maintained or improved through the use of submicron technologies, even in the presence of a reduced power supply. As a result, one of the major challenges facing MOS design engineers today is to harness the hot-carrier effects so that, without sacrificing product performance, degradation can be kept to a minimum and a reli able design obtained. To accomplish this, the physical mechanisms re sponsible for the degradations should first be experimentally identified and characterized. With adequate models thus obtained, steps can be taken to optimize the design, so that an adequate level of quality assur ance in device or circuit performance can be achieved. This book ad dresses these hot-carrier design issues for MOS devices and circuits, and is used primarily as a professional guide for process development engi neers, device engineers, and circuit designers who are interested in the latest developments in hot-carrier degradation modeling and hot-carrier reliability design techniques. It may also be considered as a reference book for graduate students who have some research interests in this excit ing, yet sometime controversial, field.
Author: Weishi Sun
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently. As device sizes shrink into the submicron region, pMOS transistor hot-carrier degradation becomes increasingly more important. There has not, however, been a widely accepted model for pMOS transistor hot-carrier degradation unlike that for nMOS transistors. Existing reliability simulations tools are primarily based on transistor level simulation and, therefore, can not handle large circuits efficiently. Using the fast-timing-based reliability simulator, ILLIADS-R, and the empirical model developed based on our experimental results, hot-carrier reliability can be well predicted. ILLIADS-R also serves as an integral part of the hierarchical design-for-reliability system. A new hot-carrier degradation model is developed for submicron pMOS transistors. Using this model, the pMOS transistor hot-carrier degradation can be predicted based on the total injected charge into the gate oxide region and the initial gate current under normal operating condition. This model is integrated into the fast-timing-based reliability simulation tool, ILLIADS-R. The simulation results demonstrate that ILLIADS-R outperforms the existing reliability simulator BERT in terms of simulation speed with a comparable accuracy. Also studied are the pMOS transistor subthreshold leakage characteristics as a function of hot-carrier stress conditions. It is shown that subthreshold leakage current is a future limit to the pMOS device lifetime.
Author: Eiji Takeda
Publisher: Academic Press
ISBN: 0126822409
Category : Juvenile Nonfiction
Languages : en
Pages : 329
Get Book Here
Book Description
The exploding number of uses for ultrafast, ultrasmall integrated circuits has increased the importance of hot-carrier effects in manufacturing as well as for other technological applications. They are rapidly movingout of the research lab and into the real world. This book is derived from Dr. Takedas book in Japanese, Hot-Carrier Effects, (published in 1987 by Nikkei Business Publishers). However, the new book is much more than a translation. Takedas original work was a starting point for developing this much more complete and fundamental text on this increasingly important topic. The new work encompasses not only all the latest research and discoveries made in the fast-paced area of hot carriers, but also includes the basics of MOS devices, and the practical considerations related to hot carriers. Chapter one itself is a comprehensive review of MOS device physics which allows a reader with little background in MOS devices to pick up a sufficient amount of information to be able to follow the rest of the book The book is written to allow the reader to learn about MOS Device Reliability in a relatively short amount of time, making the texts detailed treatment of hot-carrier effects especially useful and instructive to both researchers and others with varyingamounts of experience in the field The logical organization of the book begins by discussing known principles, then progresses to empirical information and, finally, to practical solutions Provides the most complete review of device degradation mechanisms as well as drain engineering methods Contains the most extensive reference list on the subject
Author:
Publisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 692
Get Book Here
Book Description
Author:
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
ISBN:
Category : Computers
Languages : en
Pages : 404
Get Book Here
Book Description
Author:
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 406
Get Book Here
Book Description
Author:
Publisher:
ISBN:
Category : Science
Languages : en
Pages : 1072
Get Book Here
Book Description
