Field-programmable Gate-array (FPGA) Implementation of Low-density Parity-check (LDPC) Decoder in Digital Video Broadcasting - Second Generation Satellite (DVB-S2). PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Field-programmable Gate-array (FPGA) Implementation of Low-density Parity-check (LDPC) Decoder in Digital Video Broadcasting - Second Generation Satellite (DVB-S2). PDF full book. Access full book title Field-programmable Gate-array (FPGA) Implementation of Low-density Parity-check (LDPC) Decoder in Digital Video Broadcasting - Second Generation Satellite (DVB-S2). by Kung Chi Cinnati Loi. Download full books in PDF and EPUB format.
Author: Kung Chi Cinnati Loi
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
Author: Kung Chi Cinnati Loi
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
Author: Marcos Bruno Saldanha Tavares
Publisher: Jörg Vogt Verlag
ISBN: 3938860383
Category :
Languages : en
Pages : 238
Get Book Here
Book Description
Author: Etienne Boistault
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
[ENGLISH] The aim of this project consists in the study of the error correcting codes LDPC (Low Density Parity Check) in the context of the DVB-S2 standard (Digital Video Broadcasting for Satellite version 2) in order to design a functional high-throughput decoder running on a FPGA architecture. This system would be integrated to a High Data rate Receiver; a product manufactured by Zodiac Data Systems, a French aerospace company specialized in embedded systems. This project has been divided in four parts: the first one being a literature review of the LDPC codes, DVB-S2 standard and implementations ideas. The second phase was the development of a simulator in C/C++ using Microsoft Visual Studio 6.0. Thirdly, a study has been carried out in order to develop a design that will fit inside the system, following the constraints of the FPGA architecture. In parallel, changes have been made to the simulator for it to be as close as possible to the final design and obtain reference curves. Finally, the implementation of the decoder subsystem has been started in a FPGA using the Xilinx ISE program which works with VHDL language. This document is divided into four chapters, each one explaining a specific aspect of the project. The first chapter is an introduction to the LDPC codes, to the DVB-S2 standard and to the field-programmable gate array (FPGA). Chapter two is a comprehensive study of LDPC codes and an explained selection of development choices for the implementation of the decoding along with curves obtained thanks to early versions of the simulator. The third chapter provides the details of the adaptations of the design to fit in a FPGA environment. The last chapter is focused, on the development of the FPGA blocks to execute the decoding following the specifications.
Author: Ceroici Christopher
Publisher:
ISBN:
Category :
Languages : en
Pages : 62
Get Book Here
Book Description
This thesis presents a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates. Clockless decoding increases the throughput of the decoder by eliminating the requirement for node signals to be synchronized after each decoding cycle. With this partial-update algorithm the decoder's speed is limited by the average wire delay of the interleaver rather than the worst-case delay. This type of decoder has been simulated in the past but not implemented on silicon. The design is implemented on an ALTERA Stratix IV EP4SGX230 FPGA and the frame error rate (FER) performance, throughput and power consumption are presented for (96,48) and (204,102) decoders.
Author: Edmond Nurellari
Publisher: LAP Lambert Academic Publishing
ISBN: 9783659243424
Category :
Languages : en
Pages : 136
Get Book Here
Book Description
Since the invention of Information Theory by Shannon in 1948, coding theorists have been trying to come up with coding schemes that will achieve capacity dictated by Shannon's Theorem. The most successful two coding schemes among many are the LDPCs and Turbo codes. In this thesis, we focus on LDPC codes and in particular their usage by the second generation terrestrial digital video broadcasting (DVB-T2), second generation satellite digital video broadcasting (DVB-S2) and IEEE 802.16e mobile WiMAX standards. Low Density Parity Check (LDPC) block codes were invented by Gallager in 1962 and they can achieve near Shannon limit performance on a wide variety of fading channels. LDPC codes are included in the DVB-T2 and DVB-S2 standards because of their excellent error-correcting capabilities. LDPC coding has also been adopted as an optional error correcting scheme in IEEE 802.16e mobile WiMAX. This thesis focuses on the bit error rate (BER) and PSNR performance analysis of DVB-T2, DVB-S2 and IEEE 802.16e transmission using LDPC coding under additive white Gaussian noise (AWGN) and Rayleigh Fading channel scenarios.
Author: Manpreet Singh
Publisher:
ISBN:
Category :
Languages : en
Pages : 73
Get Book Here
Book Description
Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of iterations. The design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit implementation of digit-online decoder in single-frame mode, the minimum throughput achieved is 740 Mb/s at low SNRs. For the case of 11-bit LLR digit-online decoder in frame-interlaced mode, the minimum throughput achieved is 1363 Mb/s. Detailed analysis such as effect of SNR and LLR precision on decoder power is presented. Also, the effect of changing LLR precision on max clock frequency and logic utilization on the parallel and the digit-online decoders is studied. Alongside, power per iteration for a 6-bit LLR input digit-online decoder is also reported.
Author: Monazzahalsadat Yasoubi
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
Get Book Here
Book Description
Reliable communication over noisy channel is an old but still challenging issues for communication engineers. Low density parity check codes (LDPC) are linear block codes proposed by Robert G. Gallager in 1960. LDPC codes have lesser complexity compared to Turbo-codes. In most recent wireless communication standard, LDPC is used as one of the most popular forward error correction (FEC) codes due to their excellent error-correcting capability. In this thesis we focus on hardware implementation of the LDPC used in Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) standard ratified in 2005. In architecture design of LDPC decoder, because of the structure of DVB-S2, a memory mapping scheme is used that allows 360 functional units implement simultaneously. The functional units are optimized to reduce hardware resource utilization on an FPGA. A novel design of Range addressable look up table (RALUT) for hyperbolic tangent function is proposed that simplifies the LDPC decoding algorithm while the performance remains the same. Commonly, RALUTs are uniformly distributed on input, however, in our proposed method, instead of representing the LUT input uniformly, we use a non-uniform scale assigning more values to those near zero. Zynq XC7Z030, a family of FPGA's, is used for Evaluation of the complexity of the proposed design. Synthesizes result show the speed increase due to use of LUT method, however, LUT demand more memory. Thus, we decrease the usage of resource by applying RALUT method.
Author: Alexandru Amaricai
Publisher:
ISBN:
Category : Technology
Languages : en
Pages :
Get Book Here
Book Description
Low density parity check (LDPC) decoders represent important throughput bottlenecks, as well as major cost and power-consuming components in today's digital circuits for wireless communication and storage. They present a wide range of architectural choices, with different throughput, cost, and error correction capability trade-offs. In this book chapter, we will present an overview of the main design options in the architecture and implementation of these circuits on field programmable gate array (FPGA) devices. We will present the mapping of the main units within the LDPC decoders on the specific embedded components of FPGA device. We will review architectural trade-offs for both flooded and layered scheduling strategies in their FPGA implementation.
Author:
Publisher:
ISBN:
Category : Electronic books
Languages : en
Pages : 185
Get Book Here
Book Description
This dissertation presents two-bit and three-bit quantizations for Sum Product Algorithm (SPA) decoding of Low-Density Parity-Check (LDPC) codes. The study involves evaluation of both decoding performance and hardware implementation requirements. Trade-o s be- tween these factors are considered. The quantizations are simulated in software to measure decoding performance. While quantization e ects are the focal point of the research, a comparison of the number of decoding iterations and of the number of bits of precision used in the decoder are both presented along with the quantization experiments. Decoder performance, measured in terms of both Bit Error Rate (BER) and Frame Error Rate (FER), is tested for each two-bit and three-bit quantization over a range of Signal to Noise Ratio (SNR) values. No single quantization outperforms all other quantizations for the entire tested SNR range. Analysis of the SPA is performed, revealing strategies for computational e ciency and digital design. The hardware designs combine the parity-check and variable-node update steps of the SPA into a single update computation. The update computation is implemented in a hardware design language (HDL), synthesized to programmable logic, and then tested on a Field Programmable Gate Array (FPGA). Hardware implementation requirements, as measured from the synthesis results, are evaluated and compared to a selection of other pub- lished works, particularly the work of Planjery and others A exible implementation is proposed that can adapt the quantization as the channel conditions change.
Author: Xiaoheng Chen
Publisher:
ISBN: 9781124906669
Category :
Languages : en
Pages :
Get Book Here
Book Description
Since the rediscovery of low-density parity-check (LDPC) codes in the late 1990s, tremendous progress has been made in code construction and design, decoding algorithms, and decoder implementation of these capacity-approaching codes. Recently, LDPC codes are considered for applications such as high-speed satellite and optical communications, the hard disk drives, and high-density flash memory based storage systems, which require that the codes are free of error-floor down to bit error rate (BER) as low as 10−12 to 10−15. FPGAs are usually used to evaluate the error performance of codes, since one can exploit the finite word length and extremely high internal memory bandwidth of an FPGA. Existing FPGA-based LDPC decoders fail to utilize the configurability and read-first mode of embedded memory in the FPGAs, and thus result in limited throughput and codes sizes. Four optimization techniques, i.e., vectorization, folding, message relocation, and circulant permutation matrix (CPM) sharing, are proposed to improve the throughput, scalability, and efficiency of FPGA-based decoders. Also, a semi-automatic CAD tool called QCSYN (Quasi-Cyclic LDPC decoder SYNthesis) is designed to shorten the implementation time of decoders. Using the above techniques, a high-rate (16129,15372) code is shown to have no error-floor down to the BER of 10−14. Also, it is very difficult to construct codes that do not exhibit an error floor down to 10−15 or so. Without detailed knowledge of dominant trapping sets, a backtracking-based reconfigurable decoder is designed to lower the error floor of a family of structurally compatible quasi-cyclic LDPC codes by one to two orders of magnitudes. Hardware reconfigurability is another significant feature of LDPC decoders. A tri-mode decoder for the (4095,3367) Euclidean geometry code is designed to work with three compatible binary message passing decoding algorithms. Note that this code contains 262080 edges (21.3 times of the (2048,1723) 10GBASE-T code) in its Tanner graph and is the largest code ever implemented. Besides, an efficient QC-LDPC Shift Network (QSN) is proposed to reduce the interconnect delay and control logic of circular shift network, a core component in the reconfigurable decoder that supports a family of structurally compatible codes. The interconnect delay and control logic area are reduced by a factor of 2.12 and 8, respectively. Non-binary LDPC codes are effective in combating burst errors. Using the power representation of the elements in the Galois field to organize both intrinsic and extrinsic messages, we present an efficient decoder architecture for non-binary QC-LDPC codes. The proposed decoder is reconfigurable and can be used to decode any code of a given field size. The decoder supports both regular and irregular non-binary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.
