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Author: Su Wang
Publisher:
ISBN:
Category : Electroplating
Languages : en
Pages : 190
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Book Description
Author: Su Wang
Publisher:
ISBN:
Category : Electroplating
Languages : en
Pages : 190
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Book Description
Author: Krit Athikulwongse
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages :
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Book Description
The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
Author: John H. Lau
Publisher: McGraw Hill Professional
ISBN: 0071785159
Category : Technology & Engineering
Languages : en
Pages : 513
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Book Description
A comprehensive guide to TSV and other enabling technologies for 3D integration Written by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edge information on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to highperformance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes: Nanotechnology and 3D integration for the semiconductor industry TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing TSVs: mechanical, thermal, and electrical behaviors Thin-wafer strength measurement Wafer thinning and thin-wafer handling Microbumping, assembly, and reliability Microbump electromigration Transient liquid-phase bonding: C2C, C2W, and W2W 2.5D IC integration with interposers 3D IC integration with interposers Thermal management of 3D IC integration 3D IC packaging
Author: Neha Vinayak Gaikwad
Publisher:
ISBN:
Category :
Languages : en
Pages : 24
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Book Description
In the recent years, the Through Silicon Vias (TSVs) are helping a huge variety of the 3DIC and the 2.5D IC packaging applications to try to fulfill their requirements of functionality and higher connectivity at the expense of lower power consumption and minimum heat dissipation. The TSVs offer great interconnect density, high device density, short connection paths, great space efficiency and high interconnect bandwidth. The basic difference between a 3D TSV package and a 2.5D TSV package is that the 2.5D one interconnects the dies side by side on a silicon interposer, over its entire length. The interposer, placed between the package substrate and the dies consists of the TSVs that are the interconnections between the top and bottom layers, whereas the 3D one interconnects the dies one above the other, i.e. on the top of each other. In this, the TSVs are present in the die at the bottom, which is just above the package substrate. Apart from the various advantages of the TSVs, the challenges associated with them are higher utilization of the manufacturing area and thus they ultimately result in the position barriers by securing an entire layer. Also the metal degradation impact on them, their failure dueto the environmental stresses induced in them and the overall impact of these on the entire package are also some of the challenges in TSVs, which question the reliability of the packages. In this research, a 2.5D TSV package was subjected to a thermal cycling test to investigate its reliability. For that, at first a detailed model of a 2.5D IC package is created and analyzed in ANSYS 18.0. But considering its huge number of elements and higher computational time, the compact modeling technique is implemented on it. The compact model is then subjected to thermal cycling and the output parameter thus obtained for it is compared and validated to that obtained for the detailed model.
Author: Kuan Hsun Lu
Publisher:
ISBN:
Category :
Languages : en
Pages : 250
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Book Description
This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays.
Author: Tengfei Jiang
Publisher:
ISBN:
Category :
Languages : en
Pages : 320
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Book Description
Copper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.
Author: Ehrenfried Zschech
Publisher: American Institute of Physics
ISBN: 9780735409385
Category : Science
Languages : en
Pages : 0
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Book Description
Scientist and engineers as well as graduate students in the fields of This conference will be of interest to anyone involved in Physics, Electrical Engineering, Materials Science and Engineering, Reliability and Quality Management, both in industry and academia. One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in 3D IC integration. Stresses arising in 3D TSV interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration can lead to performance reduction, reliability-limiting degradation and failure of microelectronic products. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on the device characteristics must be understood and shared, and designers need a solution for managing stress. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in 3D IC integration. Modelling and simulation capabilities as well as materials characterization are demonstrated to evaluate the effect of stress on product performance.
Author: John Lau
Publisher: McGraw Hill Professional
ISBN: 0071785140
Category : Technology & Engineering
Languages : en
Pages : 514
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Book Description
A comprehensive guide to TSV and other enabling technologies for 3D integration Written by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edge information on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to highperformance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes: Nanotechnology and 3D integration for the semiconductor industry TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing TSVs: mechanical, thermal, and electrical behaviors Thin-wafer strength measurement Wafer thinning and thin-wafer handling Microbumping, assembly, and reliability Microbump electromigration Transient liquid-phase bonding: C2C, C2W, and W2W 2.5D IC integration with interposers 3D IC integration with interposers Thermal management of 3D IC integration 3D IC packaging
Author: Xing-Chang Wei
Publisher: CRC Press
ISBN: 1315305852
Category : Computers
Languages : en
Pages : 251
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Book Description
Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging presents the electromagnetic modelling and design of three major electromagnetic compatibility (EMC) issues related to the high-speed printed circuit board (PCB) and electronic packages: signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI). The emphasis is put on two essential passive components of PCBs and packages: the power distribution network and the signal distribution network. This book includes two parts. Part one talks about the field-circuit hybrid methods used for the EMC modeling, including the modal method, the integral equation method, the cylindrical wave expansion method and the de-embedding method. Part two illustrates EMC design methods and explores the applications of novel metamaterials and two-dimensional materials on traditional EMC problems. This book is designed to enhance worthwhile electromagnetic theory and mathematical methods for practical engineers and to train students with advanced EMC applications.
Author: Nauman Khan
Publisher: Springer Science & Business Media
ISBN: 1461455073
Category : Technology & Engineering
Languages : en
Pages : 82
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Book Description
This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits. It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks. Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.
