A Study on Oxide-Semiconductor-Based Thin-Film Transistors and Memories with High-k Gate Dielectrics for System-on-Panel Applications PDF Download
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Author: 蘇迺超
Publisher:
ISBN:
Category :
Languages : en
Pages : 220
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Author: 蘇迺超
Publisher:
ISBN:
Category :
Languages : en
Pages : 220
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Author: Andre Zeumault
Publisher:
ISBN:
Category :
Languages : en
Pages : 140
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Primarily used as transparent electrodes in solar-cells, more recently, physical vapor deposited (PVD) transparent conductive oxide (TCO) materials (e.g. ZnO, In2O3 and SnO2) also serve as the active layer in thin-film transistor (TFT) technology for modern liquidcrystal displays. Relative to a-Si:H and organic TFTs, commercial TCO TFTs have reduced off-state leakage and higher on-state currents. Additionally, since they are transparent, they have the added potential to enable fully transparent TFTs which can potentially improve the power efficiency of existing displays. In addition to PVD, solution-processing is an alternative route to the production of displays and other large-area electronics. The primary advantage of solution-processing is in the ability to deposit materials at reduced-temperatures on lower-cost substrates (e.g. glass, plastics, paper, metal foils) at high speeds and over large areas. The versatility offered by solution-processing is unlike any conventional deposition process making it a highly attractive emergent technology. Unfortunately, the benefits of solution-processing are often overshadowed by a dramatic reduction in material quality relative to films produced by conventional PVD methods. Consequently, there is a need to develop methods that improve the electronic performance of solution-processed materials. Ideally, this goal can be met while maintaining relatively low processing temperatures so as to ensure compatibility with low-cost roll-compatible substrates. Mobility is a commonly used metric for assessing the electronic performance of semiconductors in terms of charge transport. It is commonly observed that TCO materials exhibit significantly higher field-effect mobility when used in conjunction with high-k gate dielectrics (10 to 100 cm2 V−1 s −1 ) as opposed to conventional thermally-grown SiO2 (0.1 to 20 cm2 V−1 s −1 ). Despite the large amount of empirical data documenting this bizarre effect, its physical ori- 2 gin is poorly understood. In this work, the interaction between semiconductor TCO films and high-k dielectrics is studied with the goal of developing a theory explaining the observed mobility enhancement. Electrical investigation suggests that the mobility enhancement is due to an effective doping of the TCO by the high-k dielectric, facilitated by donor-like defect states inadvertently introduced into the dielectric during processing. The effect these states have on electron transport in the TCO is assessed based on experimental data and electrostatic simulations and is found to correlate with negative aspects of TFT behavior (e.g. frequency dispersion, gate leakage, hysteresis, and poor bias stability). Based on these findings, we demonstrate the use of an improved device structure, analogous to the concept of modulation doping, which uses the high-k dielectric film as an encapsulate, rather than a gate-dielectric, to achieve a similar doping effect. In doing so, the enhanced mobility of the TCO/high-k interface is retained while simultaneously eliminating the negative drawbacks associated with the presence of charged defects in the gate dielectrics (e.g. frequency dispersion, gate leakage, hysteresis, and poor bias stability). This demonstrates improved understanding of the role of solution-processed high-k dielectrics in field-effect devices as well as provides a practical method to overcome the performance degradation incurred through the use of low-temperature solution-processed TCOs.
Author: Niladri Pratap Maity
Publisher: CRC Press
ISBN: 1000527441
Category : Science
Languages : en
Pages : 248
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This volume explores and addresses the challenges of high-k gate dielectric materials, one of the major concerns in the evolving semiconductor industry and the International Technology Roadmap for Semiconductors (ITRS). The application of high-k gate dielectric materials is a promising strategy that allows further miniaturization of microelectronic components. This book presents a broad review of SiO2 materials, including a brief historical note of Moore’s law, followed by reliability issues of the SiO2 based MOS transistor. It goes on to discuss the transition of gate dielectrics with an EOT ~ 1 nm and a selection of high-k materials. A review of the various deposition techniques of different high-k films is also discussed. High-k dielectrics theories (quantum tunneling effects and interface engineering theory) and applications of different novel MOSFET structures, like tunneling FET, are also covered in this book. The volume also looks at the important issues in the future of CMOS technology and presents an analysis of interface charge densities with the high-k material tantalum pentoxide. The issue of CMOS VLSI technology with the high-k gate dielectric materials is covered as is the advanced MOSFET structure, with its working structure and modeling. This timely volume will prove to be a valuable resource on both the fundamentals and the successful integration of high-k dielectric materials in future IC technology.
Author: Ngwashi Divine Khan
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Transparent oxide semiconducting films have continued to receive considerable attention, from a fundamental and application-based point of view, primarily because of their useful fundamental properties. Of particular interest is zinc oxide (ZnO), an n-type semiconductor that exhibits excellent optical, electrical, catalytic and gas-sensing properties, and has many applications in various fields. In this work, thin film transistor (TFT) arrays based on ZnO have been prepared by reactive radio frequency (RF) magnetron sputtering. Prior to the TFT fabrication, ZnO layers were sputtered on to glass and silicon substrates, and the deposition parameters optimised for electrical resistivities suitable for TFT applications. The sputtering process was carried out at room temperature with no intentional heating. The aim of this work is to prepare ZnO thin films with stable semiconducting electrical properties to be used as the active channel in TFTs; and to understand the role of intrinsic point defects in device performance and stability. The effect of oxygen (O2) adsorption on TFT device characteristics is also investigated. The structural quality of the material (defect type and concentration), electrical and optical properties (transmission/absorption) of semiconductor materials are usually closely correlated. Using the Vienna ab-initio simulation package (VASP), it is predicted that O2 adsorption may influence film transport properties only within a few atomic layers beneath the adsorption site. These findings were exploited to deposit thin films that are relatively stable in atmospheric ambient with improved TFT applications. TFTs incorporating the optimised layer were fabricated and demonstrated very impressive performance metrics, with effective channel mobilities as high as 30 cm2/V-1s-1, on-off current ratios of 107 and sub-threshold slopes of 0.9? 3.2 V/dec. These were found to be dependent on film thickness (~15? 60 nm) and the underlying dielectric (silicon dioxide (SiO2), gadolinium oxide (Gd2O3), yttrium oxide (Y2O3) and hafnium oxide (HfO2)). In this work, prior to sputtering the ZnO layer (using a ZnO target of 99.999 % purity), the sputtering chamber was evacuated to a base pressure ~4 x 10-6 Torr. Oxygen (O2) and argon (Ar) gas (with O2/Ar ratio of varying proportions) were then pumped into the chamber and the deposition process optimised by varying the RF power between 25 and 500 W and the O2/Ar ratio between 0.010 to 0.375. A two-level factorial design technique was implemented to test specific parameter combinations (i.e. RF power and O2/Ar ratio) and then statistical analysis was utilised to map out the responses. The ZnO films were sputtered on glass and silicon substrates for transparency and resistivity measurements, and TFT fabrication respectively. For TFT device fabrication, ZnO films were deposited onto thermally-grown silicon dioxide (SiO2) or a high-k dielectric layer (HfO2, Gd2O3 and Y2O3) deposited by a metal-organic chemical deposition (MOCVD) process. Also, by using ab initio simulation as implemented in the?Vienna ab initio simulation package (VASP)?, the role of oxygen adsorption on the electrical stability of ZnO thin film is also investigated. The results indicate that O2 adsorption on ZnO layers could modify both the electronic density of states in the vicinity of the Fermi level and the band gap of the film. This study is complemented by studying the effects of low temperature annealing in air on the properties of ZnO films. It is speculated that O2 adsorption/desorption at low temperatures (150? 350 0C) induces variations in the electrical resistance, band gap and Urbach energy of the film, consistent with the trends predicted from DFT results.
Author: Prem Thapaliya
Publisher:
ISBN:
Category : Flat panel displays
Languages : en
Pages : 182
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Conventional amorphous silicon based thin film transistors have been the most widely used ones for flat panel display application during the last two decades. However, the low mobility of less than 1 cm2/Vs and light induced instability of the amorphous silicon based thin film transistor make them unsuitable for high resolution displays. Oxide based thin film transistors have attracted a great deal of interest as an alternative to conventional amorphous silicon based thin film transistors for high resolution display applications. In particular, ZnO has gained considerable interest for the next generation transparent and flexible display due to its wide band gap of 3.37 eV, high electron mobility and low temperature deposition forming good quality of polycrystalline film even at room temperature. Consequently all the aforementioned features of ZnO make them promising channel material for the flexible and transparent TFTs. The electrical characteristics of ZnO based TFTs is greatly affected by the deposition condition and hence crystalline quality of channel layer, thickness of channel layer and quality of interface between the gate dielectric and the channel layer. Therefore, the deposition temperature and the thickness of the ZnO channel needs to be optimized in order to achieve high performance ZnO TFTs. Moreover, the quality of interface between the ZnO channel layer and the gate dielectric is of vital importance to improve the performance of the TFTs. In this dissertation, we have fabricated and characterized RF sputtered ZnO based thin film transistor using high-k HfO2 gate dielectric. The transparent ZnO TFTs was realized using FTO as a transparent gate electrode as opposed to commonly used ITO gate electrode. It was found that TFTs fabricated using the FTO gate electrode showed lower mobility and on/off ratio compared to the TFTs with Ru as a gate on the Si substrate. This deterioration of TFTs performance with the use of FTO gate electrode was attributed to the degradation of HfO2 gate dielectric due to the diffusion of fluorine from the FTO into the HfO2 during its deposition at 300 °C. In order to minimize the interface trap density at the interface between the ZnO and HfO2, an interfacial layer of MgO with different thickness was investigated. It was found that 10 nm MgO is an optimum thickness that can reduce the interface trap density by almost one order of magnitude and hence exhibit the best TFTs performance with field effect mobility, threshold voltage, on/off ratio and subthreshold swing to be 0.3 cm2/V.s, 3.7 V , 106 and 1.35 V/decade respectively. The decrease in the interface trap density with the interfacial layer was attributed to the reduction of defects in the ZnO by the excess oxygen ions of MgO. Furthermore, the ZnO channel layer was deposited at different temperature including room temperature, 50 °C, 100 °C and 200 °C, to determine the optimum deposition temperature that can achieve high performance ZnO TFTs. It was found that ZnO deposited at 50 °C showed the best TFT performance with field effect mobility, threshold voltage, on off ratio and subthreshold swing 1.12 cm2/V.s, 5.8 V, 1.4×105, 1.35 V/decade respectively. The improvement in the performance of the TFTs device with 50 °C ZnO was attributed to the low surface roughness of ZnO film, increased grain size and good polycrystalline quality which was confirmed with the help of XRD, AFM and SEM measurement of ZnO thin film deposited at different temperature. Likewise, once the optimum deposition temperature of ZnO was determined, the effect of ZnO thickness was investigated by depositing the ZnO with different thickness including 30 nm, 50 nm, 70 nm and 100 nm while maintaining the deposition temperature of ZnO to be at 50 °C. It was found that the TFTs device with 50 nm exhibit the superior performance over the other thicknesses of ZnO which was ascribed to the improved polycrystalline quality, low surface roughness of the 50 nm ZnO thin film.
Author: Shankar Swaminathan
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Germanium (Ge) has emerged as a promising candidate for surface channels in highly-scaled field-effect-transistors (FETs), as performance and reliability issues are likely to limit the use of conventional Si-based complementary-metal-oxide-semiconductor (CMOS) transistors beyond the 15nm technology node. Lack of a high quality and stable thermal oxide of germanium has prompted interest in the use of high-k (high dielectric-constant) gate dielectrics on Ge channels. An interface passivation layer (IPL) between the high-k film and the Ge substrate appears to be necessary to avoid large defect densities characteristic of atomically-abrupt high-k (ZrO2 or HfO2)/Ge interfaces. Atomic layer deposition (ALD) is a useful high-k metal oxide film growth technique due to the precise nature of thickness control and uniformity of thickness for ultra-thin films. The use of ALD to synthesize deposited IPLs interposed between the Ge channel and an overlying high-k layer has not been studied extensively. For this research, a laboratory-scale ALD reactor was designed and built for Al2O3 and TiO2 chemistries with liquid metal organic precursors and H2O as oxidant. A novel in situ x-ray photoelectron spectroscopy (XPS) setup that uses a differentially pumped electrons lens and analyzer was incorporated successfully into the ALD growth chamber, enabling the real-time monitoring of chemical states in the ALD ambient. This system demonstrated collection of in situ spectra within 10's of seconds of an ALD precursor pulse, without moving the substrate or changing its temperature. Pre-ALD Ge surface functionalization by in situ oxidant dosing ("pre-pulsing") in the growth chamber was studied and optimized to synthesize a high-quality ALD-Al2O3/Ge interface, with a midgap density of interface states (Dit) ~ 2x1011 cm-2 eV-1. In situ XPS studies revealed the influence of hydroxyl ( -OH) termination of the Ge surface in passivating dangling bonds that lead to fast trapping. The evolution of Ge-O bonding states during pre-pulsing was correlated with the observed improvements in hysteresis, frequency dispersion of the gate capacitance, and the response of fast (band-edge) and slow (midgap) interface states. The effects of scaling the physical thickness of the ALD-Al2O3 down to the sub-nanometer regime on key electrical parameters such as Dit, capacitance density, leakage current density and fixed charge were studied. The ultra-thin ALD-Al2O3/Ge interface, unlike in Si, was observed to resist sub-cutaneous oxidation, evidencing the capacitance scaling potential of these IPLs. Photoemission studies done using synchrotron radiation suggested a possible mechanism for FGA-induced passivation of interface states and revealed excellent valence and conduction band offsets of ALD-Al2O3 to Ge (> 2.5eV). Thus, unlike oxide or oxynitride passivation, ALD-Al2O3 IPLs promise an effective leakage barrier to hole and electron injection in addition to providing low Dit. Aggressive gate capacitance scaling requirements for future CMOS technology necessitates the use of the so-called "higher-k" dielectrics such as TiO2 (k> 25) in the gate stack. However, the conduction band offset of the TiO2/Ge interface is very low (~ 0.2eV), resulting in unacceptably high gate leakage. To this end, successful integration of ultrathin (~ 1 nm), interface-engineered ALD-Al2O3 IPLs in ALD-TiO2 gate dielectric stacks on Ge was demonstrated through detailed physical and electrical characterization studies. These IPLs, owing to their large bandgap (~ 6.6eV), were observed to dramatically reduce the gate leakage at the TiO2/Ge interface by 6 orders of magnitude at the flatband voltage. The Platinum-gated bilayer devices exhibited excellent C-V characteristics down to a CET of 1.2nm and exhibited a minimum Dit ~ 3x1011 cm-2 eV-1 near midgap after FGA. Taking into account a typical 0.4nm contribution due to the quantum capacitance of the Ge substrate, these devices are well-suited to achieve the sub-nanometer scaling benchmarks for the 22nm node and beyond. Extensive temperature- and frequency-dependent defect characterization of the bilayer devices evidenced an unpinned oxide/semiconductor interface and showed that thermally-activated electron transport into shallow defect states in the TiO2 (~0.25eV below the CB edge) near the TiO2/Al2O3 interface resulted in a temperature-dependent dispersion of the accumulation capacitance density.
Author: Danny Li-Ping Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 422
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Author: Jiang Lu
Publisher:
ISBN:
Category :
Languages : en
Pages :
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A novel high-k gate dielectric material, i.e., hafnium-doped tantalum oxide (Hf-dopedTaOx), has been studied for the application of the future generation metal-oxide semiconductor field effect transistor (MOSFET). The film's electrical, chemical, and structural properties were investigated experimentally. The incorporation of Hf into TaOx impacted the electrical properties. The doping process improved the effective dielectric constant, reduced the fixed charge density, and increased the dielectric strength. The leakage current density also decreased with the Hf doping concentration. MOS capacitors with sub-2.0 nm equivalent oxide thickness (EOT) have been achieved with the lightly Hf-doped TaOx. The low leakage currents and high dielectric constants of the doped films were explained by their compositions and bond structures. The Hf-doped TaOx film is a potential high-k gate dielectric for future MOS transistors. A 5 Å tantalum nitride (TaNx) interface layer has been inserted between the Hf-doped TaOx films and the Si substrate to engineer the high-k/Si interface layer formation and properties. The electrical characterization result shows that the insertion of a 5 Å TaNx between the doped TaOx films and the Si substrate decreased the film's leakage current density and improved the effective dielectric constant (keffective) value. The improvement of these dielectric properties can be attributed to the formation of the TaOxNy interfacial layer after high temperature O2 annealing. The main drawback of the TaNx interface layer is the high interface density of states and hysteresis, which needs to be decreased. Advanced metal nitride gate electrodes, e.g., tantalum nitride, molybdenum nitride, and tungsten nitride, were investigated as the gate electrodes for atomic layer deposition (ALD) HfO2 high-k dielectric material. Their physical and electrical properties were affected by the post metallization annealing (PMA) treatment conditions. Work functions of these three gate electrodes are suitable for NMOS applications after 800°C PMA. Metal nitrides can be used as the gate electrode materials for the HfO2 high-k film. The novel high-k gate stack structures studied in this study are promising candidates to replace the traditional poly-Si-SiO2 gate stack structure for the future CMOS technology node.
Author: Bhaswar Chakrabarti
Publisher:
ISBN:
Category : Ferroelectric storage cells
Languages : en
Pages : 346
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Floating gate transistor based flash memories have seen more than a decade of continuous growth as the prominent non-volatile memory technology. However, the recent trends indicate that the scaling of flash memory is expected to saturate in the near future. Several alternative technologies are being considered for the replacement of flash in the near future. The basic motivation for this work is to investigate the material properties of metal oxide based high-k dielectrics for potential applications in floating gate and resistance switching memory applications. This dissertation can be divided into two main sections. In the first section, the tunneling characteristics of the SiO 2 /HfO 2 stacks were investigated. Previous theoretical studies for thin SiO 2 / thick high-k stacks predict an increase in tunneling current in the high-bias regime (better programming) and a decrease in the low-bias regime (better retention) in comparison to pure SiO2 of same equivalent oxide thickness (EOT). However, our studies indicated that the performance improvement in SiO2 /HfO2 stacks with thick HfO2 layer is difficult due to significant amount of charge traps in thick HfO2 layers. Oxygen anneal on the stacks did not improve the programming current and retention. X-ray photoelectron spectroscopy (XPS) studies indicated that this was due to formation of an interfacial oxide layer. The second part of the dissertation deals with the investigation of resistive switching in metal oxides. Although promising, practical applications of resistive random access memories (RRAM) require addressing several issues including high forming voltage, large operating currents and reliability. We first investigated resistive switching in HfTiO x nanolaminate with conventional TiN electrodes. The forming-free switching observed in the structures could be described by the quantum point contact model. The modelling results indicated that the forming-free characteristics can be due to a higher number of filaments in comparison to a device that requires forming. Forming-free resistive switching with low current operation in graphene-insulator-graphene structures was also investigated. Electrical as well as Raman and XPS analysis indicated that low current operation is due to the migration and subsequent physisorption of oxygen ions on the graphene surface during the set operation. A statistical model was also developed for quantitative prediction of the effect of noise on RRAM characteristics.
Author: Jung Hwan Yum
Publisher:
ISBN:
Category :
Languages : en
Pages : 226
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The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO2 gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO2 (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x1010 eV−1cm−2), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO2 film. HfO2 based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility. High electron mobility in the III-V materials has attracted significant attention for a possible application as a channel material in metal/oxide/semiconductor (MOS) transistors. One of the main challenges is that III-V MOSFETs generally lack thermodynamically stable insulators of high electrical quality, which would passivate the interface states at the dielectric/substrate interface and unpin the Fermi level. To address this issue, various dielectric, such as Si/SiO2, Ge, SiGe, SiN and Al2O3, were considered as an interface passivation layer (IPL). Atomic Layer Deposited (ALD) Al2O3 has demonstrated superior IPL characteristics compared to the other candidates due to its high dielectric constant and interface quality. However, defect density in Al2O3 is still too high even as several cleaning methods such as NH4OH, (NH4)2S and F treatment have been developed, which limits the performance of III-V MOSFETs. In the first part of this study, theoretical approaches to understand the motivation and requirements as an high-k gate dielectric or interfacial layer, and properties of ALD beryllium oxide (BeO) for Si and III-V MOS devices have been investigated. The second part of this study focuses on the precursor synthesis and fundamental material characterization of ALD BeO thin film using physical, optical and electrical analysis. Film properties such as self-cleaning reaction and oxygen diffusion barrier will be presented. At the third part, depletion mode transistor and self-aligned MOSFETs using ALD BeO on Si and InP high mobility substrates have been investigated. And as for the final part of this study, the density functional theory of Be(CH3)2 precursor, electromagnetics, and thermodynamics were investigated to understand the reaction mechanism and self-cleaning reaction, and to evaluate the gate dielectrics such as Al2O3, BeO, SiO2, and HfO2.
