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Author: Amir Zjajo
Publisher: Springer Science & Business Media
ISBN: 9400777817
Category : Technology & Engineering
Languages : en
Pages : 207
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Book Description
One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
Author: Amir Zjajo
Publisher: Springer Science & Business Media
ISBN: 9400777817
Category : Technology & Engineering
Languages : en
Pages : 207
Get Book Here
Book Description
One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
Author: Amir Zjajo
Publisher: Springer Science & Business Media
ISBN: 9048197252
Category : Technology & Engineering
Languages : en
Pages : 311
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Book Description
With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Author: Pooyan Sakian
Publisher: Springer Science & Business Media
ISBN: 1461421225
Category : Technology & Engineering
Languages : en
Pages : 181
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Book Description
This book discusses a number of challenges faced by designers of wireless receivers, given complications caused by the shrinking of electronic and mobile devices circuitry into ever-smaller sizes and the resulting complications on the manufacturability, production yield, and the end price of the products. The authors describe the impact of process technology on the performance of the end product and equip RF designers with countermeasures to cope with such problems. The mechanisms by which these problems arise are analyzed in detail and novel solutions are provided, including design guidelines for receivers with robustness to process variations and details of circuit blocks that obtain the required performance level. Describes RF receiver frontends and their building blocks from a system- and circuit-level perspective; Provides system-level analysis of a generic RF receiver frontend with robustness to process variations; Includes details of CMOS circuit design at 60GHz and reconfigurable circuits at 60GHz; Covers millimeter-wave circuit design with robustness to process variations.
Author: Victor Champac
Publisher: Springer
ISBN: 3319754653
Category : Technology & Engineering
Languages : en
Pages : 195
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Book Description
This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
Author: Marvin Onabajo
Publisher: Springer Science & Business Media
ISBN: 1461422965
Category : Technology & Engineering
Languages : en
Pages : 183
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Book Description
This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements. Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters; Includes built-in testing techniques, linked to current industrial trends; Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches; Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.
Author: David Chinnery
Publisher: Springer Science & Business Media
ISBN: 1402071132
Category : Computers
Languages : en
Pages : 422
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Book Description
This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: Improving performance through microarchitecture; Timing-driven floorplanning; Controlling and exploiting clock skew; High performance latch-based design in an ASIC methodology; Automatically identifying and synthesizing complex logic gates; Automated cell sizing to increase performance and reduce power; Controlling process variation.These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.
Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 0387465472
Category : Technology & Engineering
Languages : en
Pages : 343
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Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Author: Ashish Raman
Publisher: CRC Press
ISBN: 1000577236
Category : Technology & Engineering
Languages : en
Pages : 410
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Book Description
This comprehensive reference text discusses novel semiconductor devices, including nanostructure field-effect transistors, photodiodes, high electron mobility transistors, and oxide-based devices. The text covers submicron semiconductor devices, device modeling, novel materials for devices, novel semiconductor devices, optimization techniques, and their application in detail. It covers such important topics as negative capacitance devices, surface-plasmon resonance devices, Fermi-level pinning, external stimuli-based optimization techniques, optoelectronic devices, and architecture-based optimization techniques. The book: Covers novel semiconductor devices with submicron dimensions Discusses comprehensive device optimization techniques Examines conceptualization and modeling of semiconductor devices Covers circuit and sensor-based application of the novel devices Discusses novel materials for next-generation devices This text will be useful for graduate students and professionals in fields including electrical engineering, electronics and communication engineering, materials science, and nanoscience.
Author: Jeroen A. Croon
Publisher: Springer Science & Business Media
ISBN: 0387243135
Category : Technology & Engineering
Languages : en
Pages : 214
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Book Description
Matching Properties of Deep Sub-Micron MOS Transistors examines this interesting phenomenon. Microscopic fluctuations cause stochastic parameter fluctuations that affect the accuracy of the MOSFET. For analog circuits this determines the trade-off between speed, power, accuracy and yield. Furthermore, due to the down-scaling of device dimensions, transistor mismatch has an increasing impact on digital circuits. The matching properties of MOSFETs are studied at several levels of abstraction: A simple and physics-based model is presented that accurately describes the mismatch in the drain current. The model is illustrated by dimensioning the unit current cell of a current-steering D/A converter. The most commonly used methods to extract the matching properties of a technology are bench-marked with respect to model accuracy, measurement accuracy and speed, and physical contents of the extracted parameters. The physical origins of microscopic fluctuations and how they affect MOSFET operation are investigated. This leads to a refinement of the generally applied 1/area law. In addition, the analysis of simple transistor models highlights the physical mechanisms that dominate the fluctuations in the drain current and transconductance. The impact of process parameters on the matching properties is discussed. The impact of gate line-edge roughness is investigated, which is considered to be one of the roadblocks to the further down-scaling of the MOS transistor. Matching Properties of Deep Sub-Micron MOS Transistors is aimed at device physicists, characterization engineers, technology designers, circuit designers, or anybody else interested in the stochastic properties of the MOSFET.
Author: Andrei Pavlov
Publisher: Springer Science & Business Media
ISBN: 1402083637
Category : Technology & Engineering
Languages : en
Pages : 203
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Book Description
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
