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Author:
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Category : Carbon nanotubes
Languages : en
Pages : 0
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Book Description
Various emerging technologies have shown great potential of supplementing silicon transistors as Moore's law slows down. One such disruptive technology, Carbon Nanotube Field Effect Transistors (CNFET), among others, promises increased speed and integration with reduced power consumption. However, due to a limited controllability over the Carbon Nano-tube(CNT) growth process, CNFETs show large variations in their performance and behavior. It is therefore difficult to predict and model their behavior while design suggestions are also challenging. CNT variations are important for a realistic delay modelling. Due to the presence of CNT-specific variations, conventional CMOS evaluation techniques cannot be used for CNFETs. Redundancy, however, comes at the cost of increased power and area. To limit redundancy, we propose adding redundant tubes only to transistors on critical paths. The challenge with this approach is that with variations, critical paths may vary under CNT variations. Therefore, to consider all potential critical paths under assumed variations and add redundancy to all of them, we developed an efficient algorithm for fast identification of all paths that can become critical in the presence of variations.
Author:
Publisher:
ISBN:
Category : Carbon nanotubes
Languages : en
Pages : 0
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Book Description
Various emerging technologies have shown great potential of supplementing silicon transistors as Moore's law slows down. One such disruptive technology, Carbon Nanotube Field Effect Transistors (CNFET), among others, promises increased speed and integration with reduced power consumption. However, due to a limited controllability over the Carbon Nano-tube(CNT) growth process, CNFETs show large variations in their performance and behavior. It is therefore difficult to predict and model their behavior while design suggestions are also challenging. CNT variations are important for a realistic delay modelling. Due to the presence of CNT-specific variations, conventional CMOS evaluation techniques cannot be used for CNFETs. Redundancy, however, comes at the cost of increased power and area. To limit redundancy, we propose adding redundant tubes only to transistors on critical paths. The challenge with this approach is that with variations, critical paths may vary under CNT variations. Therefore, to consider all potential critical paths under assumed variations and add redundancy to all of them, we developed an efficient algorithm for fast identification of all paths that can become critical in the presence of variations.
Author: Wei-Ting Chan
Publisher:
ISBN:
Category :
Languages : en
Pages : 212
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Book Description
In the past decades, device scaling along the Moore's Law trajectory has been the major focus of technology innovation in the semiconductor industry. However, this scaling has in recent years slowed down due to power limits, lithography complexity, and other physics limitations. The semiconductor industry has identified several looming technology challenges and expected new design paradigms that demand new "design-based equivalent scaling" approaches to enable continuation of Moore's Law. This thesis addresses several aspects of these challenges, for both the "More-Moore" and "More-than-Moore" domains. Interconnect reliability increases the design uncertainty in advanced node technologies. Electromigration is a growing concern in sub-22nm technology. To close a costly "chicken-egg" loop that spans library characterization and signoff in the presence of design adaptivity, we study the interlock among front-end (device) aging, voltage scaling, and electromigration; we furthermore quantify timing and power costs of meeting lifetime requirements. Based on this, we provide new signoff guidelines and demonstrate that suboptimal choice of voltage step size and scheduling strategy can result in decreased product lifetime. As semiconductor technology advances, leading-edge product companies must rapidly improve yield for designs that seek to reach mass production while still early in the adoption of a new technology node. We study the possible mitigation of yield loss by opportunistic, last-stage redundant logic insertion in early advanced-node production. We describe a yield estimation methodology, and propose an integer linear programming-based optimization of redundant logic insertion for opportunistic yield optimization. In sub-14nm processes, routability challenges arise from multiple patterning and pin access constraints that drastically weaken the correlation between global-route congestion and detailed-routing design rule violations. We present a method that applies machine learning techniques to effectively predict detailed-routing design rule violations after global routing, as well as detailed placement techniques to effectively reduce detailed-routing design rule violations. Beyond conventional design paradigms, three-dimensional integrated circuits (3DICs) with multiple tiers are expected to achieve large benefits (e.g., in terms of power and area) as compared to conventional two-dimensional designs. However, upper bounds on the potential power and area benefits from 3DIC integration with multiple tiers are not well-explored. We use the concept of implementation with infinite dimension to estimate upper bounds on power and area benefits achievable by 3DICs versus 2DICs. We observe that design power sensitivity to implementation with different dimensions correlates well with placement-based Rent parameter of the netlist. We show that the quality of netlist synthesis and optimization benefits from awareness of the target implementation dimension (e.g., 2D versus 3D). Last, aggressive requirements for low power and high performance in VLSI designs have led to increased interest in non-conventional computation paradigms. Approximate and stochastic hardware can achieve improved energy efficiency compared to accurate, traditional hardware modules. To exploit any benefits of approximate and stochastic hardware modules, design tools should be able to quickly and accurately estimate the output quality of composed approximate designs. We propose new accuracy estimation methodologies for approximate hardware and stochastic hardware, respectively. For stochastic circuits, we further investigate opportunities to optimize circuits under aggressive voltage scaling. We find that logical and physical design techniques can be combined to significantly expand the already powerful accuracy-energy tradeoff possibilities of stochastic circuits.
Author: Rasit O. Topaloglu
Publisher: Springer
ISBN: 1493921630
Category : Technology & Engineering
Languages : en
Pages : 225
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Book Description
This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance. Authors discuss in detail what are known commonly as “More than Moore” (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to “Moore's Law”. Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect.
Author: Gowrishankar Ravichandran
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 0
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Book Description
"The objective of this research is to develop an integrated design methodology for reliability and robustness. Reliability-based design (RBD) and robust design (RD) are important to obtain optimal design characterized by low probability of failure and minimum performance variations respectively. But performing both RBD and RD in a product design may be conflicting and time consuming. An integrated design model is needed to achieve both reliability and robustness simultaneously. The purpose of this thesis is to integrate reliability and robustness. To achieve this objective, we first study the general relationship between reliability and robustness. Then we perform a numerical study on the relationship between reliability and robustness, by combining the reliability based design, robust design, multi objective optimization and Taguchi's quality loss function to formulate an integrated design model. This integrated model gives reliable and robust optimum design values by minimizing the probability of failure and quality loss function of the design simultaneously. Based on the results from the numerical study, we propose a generalized quality loss function that considers both the safe region and the failure region. Taguchi's quality loss function defines quality loss in the safe design region and risk function defines quality loss in the failure region. This integrated model achieves reliability and robustness by minimizing the general quality loss function of the design. Example problems show that this methodology is computationally efficient compared to the other optimization models. Results from the various examples suggest that this method can be efficiently used to minimize the probability of failure and the total quality loss of a design simultaneously"--Abstract, p. iii
Author: Magnus Arner
Publisher: John Wiley & Sons
ISBN: 1118841956
Category : Mathematics
Languages : en
Pages : 194
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Book Description
A UNIQUELY PRACTICAL APPROACH TO ROBUST DESIGN FROM A STATISTICAL AND ENGINEERING PERSPECTIVE Variation in environment, usage conditions, and the manufacturing process has long presented a challenge in product engineering, and reducing variation is universally recognized as a key to improving reliability and productivity. One key and cost-effective way to achieve this is by robust design – making the product as insensitive as possible to variation. With Design for Six Sigma training programs primarily in mind, the author of this book offers practical examples that will help to guide product engineers through every stage of experimental design: formulating problems, planning experiments, and analysing data. He discusses both physical and virtual techniques, and includes numerous exercises and solutions that make the book an ideal resource for teaching or self-study. • Presents a practical approach to robust design through design of experiments. • Offers a balance between statistical and industrial aspects of robust design. • Includes practical exercises, making the book useful for teaching. • Covers both physical and virtual approaches to robust design. • Supported by an accompanying website (www.wiley/com/go/robust) featuring MATLAB® scripts and solutions to exercises. • Written by an experienced industrial design practitioner. This book’s state of the art perspective will be of benefit to practitioners of robust design in industry, consultants providing training in Design for Six Sigma, and quality engineers. It will also be a valuable resource for specialized university courses in statistics or quality engineering.
Author: Bo Liu
Publisher: Springer
ISBN: 3642391621
Category : Technology & Engineering
Languages : en
Pages : 243
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Book Description
Computational intelligence techniques are becoming more and more important for automated problem solving nowadays. Due to the growing complexity of industrial applications and the increasingly tight time-to-market requirements, the time available for thorough problem analysis and development of tailored solution methods is decreasing. There is no doubt that this trend will continue in the foreseeable future. Hence, it is not surprising that robust and general automated problem solving methods with satisfactory performance are needed.
Author: Guo Qi Zhang
Publisher: Springer Science & Business Media
ISBN: 0387755934
Category : Technology & Engineering
Languages : en
Pages : 338
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Book Description
In the past decades, the mainstream of microelectronics progression was mainly powered by Moore's law focusing on IC miniaturization down to nano scale. However, there is a fast increasing need for "More than Moore" (MtM) products and technology that are based upon or derived from silicon technologies, but do not simply scale with Moore’s law. This book provides new vision, strategy and guidance for the future technology and business development of micro/nanoelectronics.
Author: Jason C. Slagle
Publisher:
ISBN:
Category :
Languages : en
Pages : 139
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Book Description
Robust design methodologies are frequently utilized by organizations to develop robust and reliable complex systems. The intent of robust design is to create systems that are insensitive to variations from production, the environment, and time and use. While this process is effective, it can also be very time consuming and resource intensive for an engineering team. In addition, most robust design activity takes place at the detailed design phase, when the majority of the product life cycle cost has already been committed. Addressing robustness and the "ilities" at the architecture level may be more effective because it is the earliest and highest leverage point in the product development process. Furthermore, some system architectures are inherently more robust than others. In this thesis, a framework based on principles is proposed to architect complex systems for type I and II robustness. The principles are obtained by tracing the architectural evolution of the jet engine, which is an extremely complex system that has evolved to high reliability. This framework complements existing robust design methods, while simultaneously incorporating the robustness focus earlier in the product development process.
Author: Krishna C. Chillara
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 96
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Book Description
3D circuit integration is becoming increasingly important as one of the remaining techniques for staying on Moore's law trajectory. 3D Integrated Circuits (ICs) can be realized using the Through Silicon Via (TSV) approach. In order to extract the full benefits of 3D and for better yield, it has been suggested that the TSVs should be arranged as bundles rather than parallel TSVs. TSVs are required to route the signals through different dies in a multi-tier 3D IC. TSVs are excellent but scarce electrical conductors. Hence, it is important to utilize these resources very efficiently. In high performance 3D ICs, signaling techniques play a crucial role in determining the overall performance of the system. In this work, 3x3 and 4x4 TSV bundles are considered. Electrical parasitics of TSV bundles are extracted using Ansoft Q3D Extractor. Various techniques for signaling over TSV bundles are analyzed in this work. Performance, energy and robustness are the crucial aspects to be considered for analyzing a signaling technique. For performance analysis, maximum data rate for each of the signaling techniques is obtained and the dominant factors that determine these values are identified. 3D integration is fairly a new field and does not have common standards. Different research groups (both academic and industry) across the globe have different manufacturing technologies to suit their needs. In this work, we obtain the electrical parasitics of TSV bundles for different TSV radii ranging from 1mm to 15mm. The TSV radius for most of the 3D integration technologies falls within this range. Maximum data rates are determined for different TSV radii ranging from 1mm to 15mm. This study across different TSV radii helps in choosing a better signaling technique for a particular TSV radius depending on the design goals. Energy/bit for each of the signaling techniques is obtained for a common data rate of 10Gbps Pseudo Random Bit Sequence (PRBS) input. For robustness analysis, the impact of process, voltage and temperature variations between driver and receiver circuits is analyzed. Ansoft Q3D extractor, NCSU 45nm PDK and HSPICE simulation tool are used. From the simulation results, it is observed that a differential technique is beneficial for smaller radii in terms of maximum data rate that can be obtained. For a radius above 7mm, single ended current mode signaling gives a better data rate. Low swing single ended signaling techniques consume less energy but suffer slightly more due to process variations compared to full swing voltage mode signaling. In terms of robustness to supply noise, differential signaling is more robust compared to single ended techniques. An increase in the temperature reduces the data rates of both single ended and differential signaling techniques. Hence, depending on the TSV radius of target technology and process and environment variations, an optimum signaling technique can be chosen.
Author: Manfred Dietrich
Publisher: Springer Science & Business Media
ISBN: 1441966218
Category : Technology & Engineering
Languages : en
Pages : 261
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Book Description
Uncertainty in key parameters within a chip and between different chips in the deep sub micron area plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process. Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development. This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits. Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.
