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Author: Krit Athikulwongse
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages :
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Book Description
The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
Author: Krit Athikulwongse
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages :
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Book Description
The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.
Author: Sung Kyu Lim
Publisher: Springer Science & Business Media
ISBN: 1441995420
Category : Technology & Engineering
Languages : en
Pages : 573
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Book Description
This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
Author:
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 168
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Book Description
Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage. The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function. The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance. Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects. This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential. A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
Author:
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 150
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Book Description
Through-silicon via (TSV)-based three-dimensional integrated circuits (3D ICs) are expected to be the breakthrough technology for keeping up with the scaling trends of Moore's law, while also offering the unique opportunity for functional diversification through heterogenous integration. TSVs are vertical metal interconnects enabling communication across stacked and thinned dies. The dramatic reduction in global wirelength and chip footprint in 3DICs, directly improves delay, device density, bandwidth and routing congestion. Even with the current maturation of TSV process, the roadmap for industry adoption of 3DICs remains largely uncertain due to lack of standardized 3D tools capable of handling the sheer complexity of the three-dimensional solution space. Many critical design issues arise due to usage of TSVs. Large-sized TSVs, introduce significant area and delay overhead. The increased risk of TSV failure during fabrication or bonding, causes long-term reliability issues and loss of yield. The earlier these critical issues are addressed in the design cycle, the better our chances are of making realistic performance predictions and informed decisions, for speeding-up convergence. 3D floorplanning constitutes an important first step of layout design, providing early feedback on critical performance metrics, i.e., area, wirelength, delay, power and wiring density. Since the resulting floorplan impacts the optimization of all subsequent stages, there is a critical need for efficient TSV-aware layout design exploration tools, which can accurately characterize the physical and electrical impact of TSVs. A key concept of this thesis is that interconnect performance in 3D chips is directly controlled by the quality of the generated 3D floorplan, which is fundamentally impacted by the heuristics guiding the search and evaluation of floorplan. In support of this view, the core objective of this thesis is to develop an efficient methodology to improve the 3D floorplan solution quality. By generating more realistic 3D layouts, we seek to improve the accuracy of evaluation of the goodness of a 3D floorplan. A new dynamic TSV clustering algorithm is introduced, which simultaneously optimizes the sizes and positions of TSV clusters on the layout. This is the first work to consider the direct minimization of TSV occupied area at the floorplanning stage. As the generated floorplan is independent of any fixed arrangement of TSVs as input, it facilitates a more realistic and accurate evaluation of floorplan metrics. A novel nets-to-TSVs assignment algorithm which considers the inherent trade-off between TSV area and the TSV capacitance during net delay optimization, is also included. Experimental results with GSRC benchmarks show average 25% reduction in TSV footprint for all benchmarks, as compared to the single TSV placement approach. Compared to floorplanning with fixed-sized TSV islands, the approach reduces total chip area by average 7.6% and total interconnect delay by average 9%.
Author: Aida Todri-Sanial
Publisher: CRC Press
ISBN: 1351830198
Category : Technology & Engineering
Languages : en
Pages : 409
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Book Description
Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.
Author: Manho Lee
Publisher: Springer
ISBN: 9401790388
Category : Technology & Engineering
Languages : en
Pages : 286
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Book Description
Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep into TSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered.
Author: Dae Hyun Kim
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages :
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Book Description
The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.
Author: Khaled Salah
Publisher: Springer
ISBN: 3319076116
Category : Technology & Engineering
Languages : en
Pages : 181
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Book Description
This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor and inductive-based communication system and bandpass filtering.
Author: Brandon Noia
Publisher: Springer
ISBN: 9783319345345
Category : Technology & Engineering
Languages : en
Pages : 0
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Book Description
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Author: 唐紹祐
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
