Author: Hans-Oliver Joachim
Publisher:
ISBN: 9783826512285
Category : Integrated circuits
Languages : en
Pages : 202
Book Description
Investigation on the Short Channel Silicon on Insulator (SOI) MOSFET Towards 0,1 _m63m [mym] Gate Length for Future VLSI Applications
Author: Hans-Oliver Joachim
Publisher:
ISBN: 9783826512285
Category : Integrated circuits
Languages : en
Pages : 202
Book Description
Publisher:
ISBN: 9783826512285
Category : Integrated circuits
Languages : en
Pages : 202
Book Description
Silicon-on-Insulator Technology
Author: J.-P. Colinge
Publisher: Springer Science & Business Media
ISBN: 1475721218
Category : Technology & Engineering
Languages : en
Pages : 236
Book Description
5. 2. Distinction between thick- and thin-film devices . . . . . . . . . . . . . . . . . . . . 109 5. 3. I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5. 3. 1. Threshold voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 5. 3 . 2. Body effecL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 5. 3. 3. Short-channel effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5. 3. 4. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 5. 4. Transconductance and mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5. 4. 1 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5. 4. 2. Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5. 5. Subthreshold slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5. 6. Impact ionization and high-field effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 5. 6. 1. Kink effecL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 5. 6. 2. Hot-electron degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5. 7. Parasitic bipolar effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5. 7. 1. Anomalous subthreshold slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 45 5. 7. 2. Reduced drain breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 5. 8. Accumulation-mode p-channel MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 CHAPTER 6 - Other SOl Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 6. 1. Non-conventional devices adapted from bulk . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6. 1. 1. COMFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6. 1. 2. High-voltage lateral MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 6. 1. 3. PIN photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6. 1. 4. JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6. 2. Novel SOl devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6. 2. 1. Lubistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6. 2. 2. Bipolar-MOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6. 2. 3. Double-gate MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 69 6. 2. 4. Bipolar transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6. 2. 5. Optical modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 74 CHAPTER 7 - The sm MOSFET Operating in a Harsh Environment. . . . . . . . 1 77 7. 1. Radiation environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 7 7. 1. 1. SEU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7. 1. 2. Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7. 1. 3. Dose-rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4 7. 2. High-temperature operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 7. 2. 1. Leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Publisher: Springer Science & Business Media
ISBN: 1475721218
Category : Technology & Engineering
Languages : en
Pages : 236
Book Description
5. 2. Distinction between thick- and thin-film devices . . . . . . . . . . . . . . . . . . . . 109 5. 3. I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5. 3. 1. Threshold voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 5. 3 . 2. Body effecL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 5. 3. 3. Short-channel effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5. 3. 4. Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 5. 4. Transconductance and mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5. 4. 1 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5. 4. 2. Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5. 5. Subthreshold slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 5. 6. Impact ionization and high-field effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 5. 6. 1. Kink effecL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 39 5. 6. 2. Hot-electron degradation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 5. 7. Parasitic bipolar effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5. 7. 1. Anomalous subthreshold slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 45 5. 7. 2. Reduced drain breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 5. 8. Accumulation-mode p-channel MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 CHAPTER 6 - Other SOl Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 9 6. 1. Non-conventional devices adapted from bulk . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 6. 1. 1. COMFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6. 1. 2. High-voltage lateral MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 1 6. 1. 3. PIN photodiode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6. 1. 4. JFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 6. 2. Novel SOl devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6. 2. 1. Lubistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6. 2. 2. Bipolar-MOS device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6. 2. 3. Double-gate MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 69 6. 2. 4. Bipolar transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 6. 2. 5. Optical modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 74 CHAPTER 7 - The sm MOSFET Operating in a Harsh Environment. . . . . . . . 1 77 7. 1. Radiation environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 7 7. 1. 1. SEU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7. 1. 2. Total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7. 1. 3. Dose-rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4 7. 2. High-temperature operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 85 7. 2. 1. Leakage currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Silicon-on-insulator (SOI) MOSFETs
Author: Ji'an Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 390
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 390
Book Description
Design, Simulation and Analysis of the Switching and RF Performance of Multi-gate Silicon-on-insulator Mosfet Device Structures
Author: Aniket A. Breed
Publisher:
ISBN:
Category :
Languages : en
Pages : 362
Book Description
Silicon-only MOSFETs have fast approached their scaling limitations and new technologies are constantly being investigated with an intention to replace the planar silicon-only MOSFET. The Silicon-on-Insulator (SOI) technology is the forerunner in many such ongoing investigations. Devices fabricated using this technology exhibit reduced junction capacitances, lower leakage currents and higher ease of integration when scaled into the sub-nanometer regime. With the advent of novel and reliable fabrication techniques, multi-gate SOI devices viz. the FinFET, TriGate, Omega-gate and Quadruple gate MOSFETs are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. This study examines the switching and RF performance of these multi-gate devices under aggressive scaling conditions with the aid of three dimensional numerical simulations. The primary focus of investigation is a variation in the subthreshold device performance when subjected to a change in dimensions. Also investigated are the effects of variation in the lengths of the extension and LDD regions on the subthreshold device performance of these multi-gate MOSFETS. The study also includes an analysis of the subthreshold behavior under high temperature conditions. Most importantly, this study investigates the microwave performance of the devices via a simulation analysis of their small-signal behavior. The variation in the microwave performance of these devices is further extended to include the effects of variation in the length of the extension regions on the RF device performance. In conjunction with N-channel devices, the study also focuses on P-channel devices and compares the performances of the two. Out of the four multi-gate SOI device structures, the FinFET and the TriGate appear to be the most promising alternatives to replace the conventional MOSFET in future applications.
Publisher:
ISBN:
Category :
Languages : en
Pages : 362
Book Description
Silicon-only MOSFETs have fast approached their scaling limitations and new technologies are constantly being investigated with an intention to replace the planar silicon-only MOSFET. The Silicon-on-Insulator (SOI) technology is the forerunner in many such ongoing investigations. Devices fabricated using this technology exhibit reduced junction capacitances, lower leakage currents and higher ease of integration when scaled into the sub-nanometer regime. With the advent of novel and reliable fabrication techniques, multi-gate SOI devices viz. the FinFET, TriGate, Omega-gate and Quadruple gate MOSFETs are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. This study examines the switching and RF performance of these multi-gate devices under aggressive scaling conditions with the aid of three dimensional numerical simulations. The primary focus of investigation is a variation in the subthreshold device performance when subjected to a change in dimensions. Also investigated are the effects of variation in the lengths of the extension and LDD regions on the subthreshold device performance of these multi-gate MOSFETS. The study also includes an analysis of the subthreshold behavior under high temperature conditions. Most importantly, this study investigates the microwave performance of the devices via a simulation analysis of their small-signal behavior. The variation in the microwave performance of these devices is further extended to include the effects of variation in the length of the extension regions on the RF device performance. In conjunction with N-channel devices, the study also focuses on P-channel devices and compares the performances of the two. Out of the four multi-gate SOI device structures, the FinFET and the TriGate appear to be the most promising alternatives to replace the conventional MOSFET in future applications.
A Design Study on the Scaling Limit of Ultra-thin Silicon-on-insulator MOSFETs
Author: Wei-Yuan Lu
Publisher:
ISBN: 9781109879605
Category :
Languages : en
Pages : 124
Book Description
As bulk CMOS is approaching its scaling limit, SOI CMOS is gaining more and more attentions and is considered as a potential candidate for achieving 10-nm CMOS. Fully-depleted SOI MOSFETs have several inherent advantages over bulk MOSFETs-low junction capacitance, no body effect and no need for body doping to confine gate depletion. This dissertation presents a comprehensive, 2-D simulation-based design study on the scaling limit of ultra-thin silicon-on-insulator MOSFETs.
Publisher:
ISBN: 9781109879605
Category :
Languages : en
Pages : 124
Book Description
As bulk CMOS is approaching its scaling limit, SOI CMOS is gaining more and more attentions and is considered as a potential candidate for achieving 10-nm CMOS. Fully-depleted SOI MOSFETs have several inherent advantages over bulk MOSFETs-low junction capacitance, no body effect and no need for body doping to confine gate depletion. This dissertation presents a comprehensive, 2-D simulation-based design study on the scaling limit of ultra-thin silicon-on-insulator MOSFETs.
Device Design of Sub-100nm Fully-depleted Silicon-on-Insulator (SOI) Devices Based on High-k Epitaxial-Buried Oxide
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. The era of planar bulk MOS transistor, however, is nearing its end. The performance of bulk MOS transistor is severely degraded by short channel effects in the sub-65nm regime. In such a scenario, the Silicon-on-Insulator (SOI) technology looks set to become the next driver of CMOS scaling. SOI has been proved capable of providing increased transistor speed, reduced power consumption and enhanced device scalability as demanded by the 65nm and beyond technology generations. The problems facing SOI include fabrication of thin silicon and buried oxide (BOX) films and high manufacturing cost. This thesis focuses on a novel approach to building a SOI substrate which uses an epitaxial oxide as template to grow silicon on top. The novel "Floating Epitaxy SOI" aims to guarantee thin silicon films and low manufacturing cost. This research work involves modeling ultra-thin body fully depleted SOI devices from 60nm gate length down to 10nm gate length. The device uses metalD igh-k gatestack and strained silicon as attractive features for better device performance. The goal of this work is to re-engineer the device structure and alter device design parameters at every gate length such that device performance meets the semiconductor roadmap projections in terms of off-state leakage current and ratio of drive current to leakage current as specified by International Technology Roadmap for Semiconductors. (ITRS) A challenge to better device performance is the high permittivity of candidate epitaxial oxides. It is well established that high permittivity buried oxide layer adds additional short channel effects. This makes device design and control of short channel effects more difficult. The major findings of this thesis are that ultra-thin body SOI devices based on "Floating Epitaxy SOI" meet ITRS projections down to 10nm gate length. Moreover, for sub-15nm devices that require ult.
Publisher:
ISBN:
Category :
Languages : en
Pages :
Book Description
The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. The era of planar bulk MOS transistor, however, is nearing its end. The performance of bulk MOS transistor is severely degraded by short channel effects in the sub-65nm regime. In such a scenario, the Silicon-on-Insulator (SOI) technology looks set to become the next driver of CMOS scaling. SOI has been proved capable of providing increased transistor speed, reduced power consumption and enhanced device scalability as demanded by the 65nm and beyond technology generations. The problems facing SOI include fabrication of thin silicon and buried oxide (BOX) films and high manufacturing cost. This thesis focuses on a novel approach to building a SOI substrate which uses an epitaxial oxide as template to grow silicon on top. The novel "Floating Epitaxy SOI" aims to guarantee thin silicon films and low manufacturing cost. This research work involves modeling ultra-thin body fully depleted SOI devices from 60nm gate length down to 10nm gate length. The device uses metalD igh-k gatestack and strained silicon as attractive features for better device performance. The goal of this work is to re-engineer the device structure and alter device design parameters at every gate length such that device performance meets the semiconductor roadmap projections in terms of off-state leakage current and ratio of drive current to leakage current as specified by International Technology Roadmap for Semiconductors. (ITRS) A challenge to better device performance is the high permittivity of candidate epitaxial oxides. It is well established that high permittivity buried oxide layer adds additional short channel effects. This makes device design and control of short channel effects more difficult. The major findings of this thesis are that ultra-thin body SOI devices based on "Floating Epitaxy SOI" meet ITRS projections down to 10nm gate length. Moreover, for sub-15nm devices that require ult.
Modeling Independent-double-gate Silicon-on-insulator (IDG SOI) MOSFET
Author: Sudheer Vootkuri
Publisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 168
Book Description
Publisher:
ISBN:
Category : Field-effect transistors
Languages : en
Pages : 168
Book Description
Silicon-on-insulator (SOI)
Author: Bilal Abd al-Rahman
Publisher:
ISBN:
Category : Silicon-on-insulator technology
Languages : en
Pages : 27
Book Description
Publisher:
ISBN:
Category : Silicon-on-insulator technology
Languages : en
Pages : 27
Book Description
Investigation of Silicon-on-insulator Materials and Devices for VLSI and Special-device Applications
Author: Hung-Sheng Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 304
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 304
Book Description
Silicon-On-Insulator Technology: Materials To Vlsi, 3E
Author: Colinge
Publisher:
ISBN: 9788181288967
Category :
Languages : en
Pages : 384
Book Description
Publisher:
ISBN: 9788181288967
Category :
Languages : en
Pages : 384
Book Description