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Author: Alexios Konstantinos Balatsoukas Stimming
Publisher:
ISBN:
Category :
Languages : en
Pages : 162
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Book Description
Mots-clés de l'auteur: polar codes ; successive cancellation list decoding ; hardware implementation ; VLSI ; approximate computing ; faulty decoding ; LDPC codes ; unrolled decoding.
Author: Alexios Konstantinos Balatsoukas Stimming
Publisher:
ISBN:
Category :
Languages : en
Pages : 162
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Book Description
Mots-clés de l'auteur: polar codes ; successive cancellation list decoding ; hardware implementation ; VLSI ; approximate computing ; faulty decoding ; LDPC codes ; unrolled decoding.
Author: Pascal Giard
Publisher: Springer
ISBN: 3319597825
Category : Computers
Languages : en
Pages : 108
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Book Description
A new class of provably capacity achieving error-correction codes, polar codes are suitable for many problems, such as lossless and lossy source coding, problems with side information, multiple access channel, etc. The first comprehensive book on the implementation of decoders for polar codes, the authors take a tutorial approach to explain the practical decoder implementation challenges and trade-offs in either software or hardware. They also demonstrate new trade-offs in latency, throughput, and complexity in software implementations for high-performance computing and GPGPUs, and hardware implementations using custom processing elements, full-custom application-specific integrated circuits (ASICs), and field-programmable-gate arrays (FPGAs). Presenting a good overview of this research area and future directions, High-Speed Decoders for Polar Codes is perfect for any researcher or SDR practitioner looking into implementing efficient decoders for polar codes, as well as students and professors in a modern error correction class. As polar codes have been accepted to protect the control channel in the next-generation mobile communication standard (5G) developed by the 3GPP, the audience includes engineers who will have to implement decoders for such codes and hardware engineers designing the backbone of communication networks.
Author: Aliazam Abbasfar
Publisher: Springer Science & Business Media
ISBN: 1402063911
Category : Technology & Engineering
Languages : en
Pages : 94
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Book Description
This book introduces turbo error correcting concept in a simple language, including a general theory and the algorithms for decoding turbo-like code. It presents a unified framework for the design and analysis of turbo codes and LDPC codes and their decoding algorithms. A major focus is on high speed turbo decoding, which targets applications with data rates of several hundred million bits per second (Mbps).
Author: Vikram Arkalgud Chandrasetty
Publisher: Academic Press
ISBN: 0128112565
Category : Technology & Engineering
Languages : en
Pages : 192
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Book Description
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation How to reduce computational complexity and power consumption using computer aided design techniques All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs Provides extensive treatment of LDPC decoding algorithms and hardware implementations Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis
Author: Zhiqiang Cui
Publisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 218
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Book Description
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g., N>1000 bits), which lead to a linear increase of the size of memory for storing all the soft messages in LDPC decoding. In the next generation communication systems, the target data rates range from a few hundred Mbit/sec to several Gbit/sec. To achieve those very high decoding throughput, a large amount of computation units are required, which will significantly increase the hardware cost and power consumption of LDPC decoders. LDPC codes are decoded using iterative decoding algorithms. The decoding latency and power consumption are linearly proportional to the number of decoding iterations. A decoding approach with fast convergence speed is highly desired in practice. This thesis considers various VLSI design issues of LDPC decoder and develops efficient approaches for reducing memory requirement, low complexity implementation, and high speed decoding of LDPC codes. We propose a memory efficient partially parallel decoder architecture suited for quasi-cyclic LDPC (QC-LDPC) codes using Min-Sum decoding algorithm. We develop an efficient architecture for general permutation matrix based LDPC codes. We have explored various approaches to linearly increase the decoding throughput with a small amount of hardware overhead. We develop a multi-Gbit/sec LDPC decoder architecture for QC-LDPC codes and prototype an enhanced partially parallel decoder architecture for a Euclidian geometry based LDPC code on FPGA. We propose an early stopping scheme and an extended layered decoding method to reduce the number of decoding iterations for undecodable and decodable sequence received from channel. We also propose a low-complexity optimized 2-bit decoding approach which requires comparable implementation complexity to weighted bit flipping based algorithms but has much better decoding performance and faster convergence speed.
Author: Seyyed Ali Hashemi
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Polar codes have received a great deal of attention in the past few years to the extent that they are selected to be included in the 5th Generation of Wireless Communications Standard (5G). Specifically, polar codes were selected as the coding scheme for the Enhanced Mobile Broadband (eMBB) control channel which requires codes of short length. The main bottleneck in the deployment of polar codes in 5G is the design of a decoder which can achieve good error-correction performance, with low hardware implementation cost and high throughput. Successive-Cancellation (SC) decoding was the first algorithm under which polar codes could achieve capacity when the code length is very high. However, for finite practical code lengths, SC decoding falls short in providing a reasonable error-correction performance because of its sub-optimality with respect to the Maximum-Likelihood (ML) decoder. Sphere Decoding (SD) is an algorithm that can achieve the performance of ML decoding with a very high complexity. In order to close the gap between SC and ML decoding, Successive-Cancellation List (SCL) decoding keeps a list of candidates and selects the one with the best Path Metric (PM). Although SCL provides a good error-correction performance, it comes at the cost of higher complexity and lower throughput. In this thesis, we first propose a low complexity SD algorithm which provides a good trade-off between the error-correction performance and the complexity of the decoder for polar codes of short lengths. We then propose algorithms to speed up the SCL decoders. We prove that while these algorithms have much higher throughput than the conventional SCL decoder, they incur no error-correction performance loss. We further propose several techniques to reduce the area occupation in the hardware implementation of SC and SCL decoders by reducing their memory requirements. We solve the flexibility issue of fast SC-based decoders and introduce a completely rate-flexible scheme. Hardware architectures for the proposed algorithms are presented and comparisons with state of the art are made. Finally, we evaluate the performance of polar codes in 5G and we show that polar codes can be used in practical applications by proposing a blind detection scheme with polar codes." --
Author: Xiaoheng Chen
Publisher:
ISBN: 9781124906669
Category :
Languages : en
Pages :
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Book Description
Since the rediscovery of low-density parity-check (LDPC) codes in the late 1990s, tremendous progress has been made in code construction and design, decoding algorithms, and decoder implementation of these capacity-approaching codes. Recently, LDPC codes are considered for applications such as high-speed satellite and optical communications, the hard disk drives, and high-density flash memory based storage systems, which require that the codes are free of error-floor down to bit error rate (BER) as low as 10−12 to 10−15. FPGAs are usually used to evaluate the error performance of codes, since one can exploit the finite word length and extremely high internal memory bandwidth of an FPGA. Existing FPGA-based LDPC decoders fail to utilize the configurability and read-first mode of embedded memory in the FPGAs, and thus result in limited throughput and codes sizes. Four optimization techniques, i.e., vectorization, folding, message relocation, and circulant permutation matrix (CPM) sharing, are proposed to improve the throughput, scalability, and efficiency of FPGA-based decoders. Also, a semi-automatic CAD tool called QCSYN (Quasi-Cyclic LDPC decoder SYNthesis) is designed to shorten the implementation time of decoders. Using the above techniques, a high-rate (16129,15372) code is shown to have no error-floor down to the BER of 10−14. Also, it is very difficult to construct codes that do not exhibit an error floor down to 10−15 or so. Without detailed knowledge of dominant trapping sets, a backtracking-based reconfigurable decoder is designed to lower the error floor of a family of structurally compatible quasi-cyclic LDPC codes by one to two orders of magnitudes. Hardware reconfigurability is another significant feature of LDPC decoders. A tri-mode decoder for the (4095,3367) Euclidean geometry code is designed to work with three compatible binary message passing decoding algorithms. Note that this code contains 262080 edges (21.3 times of the (2048,1723) 10GBASE-T code) in its Tanner graph and is the largest code ever implemented. Besides, an efficient QC-LDPC Shift Network (QSN) is proposed to reduce the interconnect delay and control logic of circular shift network, a core component in the reconfigurable decoder that supports a family of structurally compatible codes. The interconnect delay and control logic area are reduced by a factor of 2.12 and 8, respectively. Non-binary LDPC codes are effective in combating burst errors. Using the power representation of the elements in the Galois field to organize both intrinsic and extrinsic messages, we present an efficient decoder architecture for non-binary QC-LDPC codes. The proposed decoder is reconfigurable and can be used to decode any code of a given field size. The decoder supports both regular and irregular non-binary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.
Author: Alexandre Raymond
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Polar codes are a new class of forward error-correcting codes recently discovered by Arıkan. They are the first codes with an explicit construction to provably achieve capacity, a theoretical limit governing the transmission of information in the presence of noise, for a wide variety of communication channels. Since polar codes have a very regular construction, they also lend themselves very well to hardware implementations. This thesis presents the design work underlying the development of two generations of hardware decoders for polar codes based upon the successive-cancellation algorithm. Making use of SRAM-based semi-parallel architectures, those designs allow very large polar codes to be implemented on Altera Stratix IV and Stratix V FPGA targets: up to N=2 17 for the first generation, and N=2 21 for the second-generation design. The second-generation decoder also features variable quantization levels to reduce its memory footprint, look-ahead to improve throughput, a redesigned partial-sum encoder based on a novel semi-parallel design for increased scalability, and an overlapped frame loading mechanism allowing full-speed operation of the decoder with a single input buffer." --
Author: Yuta Toriyama
Publisher:
ISBN:
Category :
Languages : en
Pages : 133
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Book Description
Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency. We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.
Author: Tinoosh Mohsenin
Publisher:
ISBN: 9781124509181
Category :
Languages : en
Pages :
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Book Description
Many emerging and future communication applications require a significant amount of high throughput data processing and operate with decreasing power budgets. This need for greater energy efficiency and improved performance of electronic devices demands a joint optimization of algorithms, architectures, and implementations. Low Density Parity Check (LDPC) decoding has received significant attention due to its superior error correction performance, and has been adopted by recent communication standards such as 10GBASE-T 10 Gigabit Ethernet. Currently high performance LDPC decoders are designed to be dedicated blocks within a System-on-Chip (SoC) and require many processing nodes. These nodes require a large set of interconnect circuitry whose delay and power are wire-dominated circuits. Therefore, low clock rates and increased area are a common result of the codes' inherent irregular and global communication patterns. As the delay and energy costs caused by wires are likely to increase in future fabrication technologies new solutions dealing with future VLSI challenges must be considered. Three novel message-passing decoding algorithms, Split-Row, Multi-Splitand Split-Row Threshold are introduced, which significantly reduce processor logical complexity and local and global interconnections. One conventional and four Split-Row Threshold LDPC decoders compatible with the 10GBASE-T standard are implemented in 65 nm CMOS and presented along with their trade-offs in error correction performance, wire interconnect complexity, decoder area, power dissipation, and speed. For additional power saving, an adaptive wordwidth decoding algorithm is proposed which switches between a 6-bit Normal Mode and a reduced 3-bit Low Power Mode depending on the SNR and decoding iteration. A 16-way Split-Row Threshold with adaptive wordwidth implementation achieves improvements in area, throughput and energy efficiency of 3.9x, 2.6x, and 3.6x respectively, compared to a MinSum Normalized implementation, with an SNR loss of 0.25 dB at BER = 10−7. The decoder occupies a die area of 5.10 mm2, operates up to 185 MHz at 1.3 V, and attains an average throughput of 85.7 Gbps with early-termination. Low power operation at 0.6 V gives a worst case throughput of 9.3 Gbps--above the 6.4 Gbps 10GBASE-T requirement, and an average power of 31 mW.
