Author:
Publisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 1018
Book Description
Scientific and Technical Aerospace Reports
Author:
Publisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 1018
Book Description
Publisher:
ISBN:
Category : Aeronautics
Languages : en
Pages : 1018
Book Description
Génération de test de circuits intégrés fondée sur des modèles fonctionnels (Generation of integrated circuits founded on functional models)
Author: M. Karam
Publisher:
ISBN:
Category :
Languages : fr
Pages : 0
Book Description
Publisher:
ISBN:
Category :
Languages : fr
Pages : 0
Book Description
Government Reports Annual Index
Author:
Publisher:
ISBN:
Category : Research
Languages : en
Pages : 1290
Book Description
Sections 1-2. Keyword Index.--Section 3. Personal author index.--Section 4. Corporate author index.-- Section 5. Contract/grant number index, NTIS order/report number index 1-E.--Section 6. NTIS order/report number index F-Z.
Publisher:
ISBN:
Category : Research
Languages : en
Pages : 1290
Book Description
Sections 1-2. Keyword Index.--Section 3. Personal author index.--Section 4. Corporate author index.-- Section 5. Contract/grant number index, NTIS order/report number index 1-E.--Section 6. NTIS order/report number index F-Z.
Functional Test Pattern Generation for Integrated Circuits
Author: Ramin Khorram
Publisher:
ISBN:
Category :
Languages : en
Pages : 142
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 142
Book Description
Government Reports Announcements & Index
Author:
Publisher:
ISBN:
Category : Science
Languages : en
Pages : 658
Book Description
Publisher:
ISBN:
Category : Science
Languages : en
Pages : 658
Book Description
Analysis and Modeling Methods for Predicting Functional Robustness of Integrated Circuits During Fast Transient Events
Author: Rémi Bèges
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges.
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Miniaturization of electronic circuits continues nowadays with the more recent technology nodes being applied to diverse fields of application such as automotive. Very dense and small integrated circuits are interesting for economic reasons, because they are cheaper to manufacture in mass and can pack more functionalities with elevated performances. The counterpart of size reduction is integrated circuits becoming more fragile electrically. In the automotive world, the new trend of fully autonomous driving is seeing tremendous progress recently. Autonomous vehicles must take decisions and perform critical actions such as braking or steering the wheel. Those decisions are taken by electronic modules, that have now very high responsibilities with regards of our safety. It is important to ensure that those modules will operate no matter the kind of disturbances they can be exposed to. The automotive world is a quite harsh environment for electronic systems. A major source of electrical stress is called the Electrostatic Discharge (ESD). It is a very sudden flow of electricity of large amplitude capable of destroying electronic components, or disturb them during their normal operation. This research focuses on functional failures where functionality can be temporarily lost after an ESD with various impact on the vehicle. To guarantee before manufacturing that a module and its components will perform their duty correctly, new analysis and prediction methods are required against soft-failures caused by electrostatic discharges. In this research, different approaches have been explored and proposed towards that goal. First, a modelling method for reproducing the ESD waveforms from the test generator up to the integrated circuit input is presented. It is based on a hierarchical approach where each element of the system is modelled individually, then added to the complete setup model. A practical case of functional failure at silicon-level is analyzed using simulation tools. To acquire more data on this fault, a testchip has been designed. It contains on-chip monitoring structures to measure voltage and current, and monitor function behavior directly at silicon-level. The last part of this research details different analysis methods developed for identifying efficiently functional weaknesses. The methods rely heavily on simulation tools, and prototypes have been implemented to prove the initial concepts. The first method models each function inside the chip individually, using behavioral models, then enables to connect the models together to deduce the full function's robustness. It enables hierarchical analysis of complex integrated circuit designs, to identify potential weak spots inside the circuit that could require more shielding or protection. The second method is focused on constructing equivalent electrical black box models of integrated circuit functions. The goal is to model the IC with a behavioral, black-box model capable of reproducing waveforms in powered conditions during the ESD. In summary, this research work has led to the development of several hardware and software prototypes. It has also highlighted important modelling challenges to solve in future works to achieve better functional robustness against electrostatic discharges.
Functional Simulation for Test Vector Generation of a Very Large Scale Integrated Circuit
Author: Yongyut Yuenyongsgool
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 412
Book Description
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 412
Book Description
Models for Large Integrated Circuits
Author: Patrick DeWilde
Publisher: Springer
ISBN: 9781461288336
Category : Technology & Engineering
Languages : en
Pages : 220
Book Description
A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned.
Publisher: Springer
ISBN: 9781461288336
Category : Technology & Engineering
Languages : en
Pages : 220
Book Description
A modern microelectronic circuit can be compared to a large construction, a large city, on a very small area. A memory chip, a DRAM, may have up to 64 million bit locations on a surface of a few square centimeters. Each new generation of integrated circuit- generations are measured by factors of four in overall complexity -requires a substantial increase in density from the current technology, added precision, a decrease of the size of geometric features, and an increase in the total usable surface. The microelectronic industry has set the trend. Ultra large funds have been invested in the construction of new plants to produce the ultra large-scale circuits with utmost precision under the most severe conditions. The decrease in feature size to submicrons -0.7 micron is quickly becoming availabl- does not only bring technological problems. New design problems arise as well. The elements from which microelectronic circuits are build, transistors and interconnects, have different shape and behave differently than before. Phenomena that could be neglected in a four micron technology, such as the non-uniformity of the doping profile in a transistor, or the mutual capacitance between two wires, now play an important role in circuit design. This situation does not make the life of the electronic designer easier: he has to take many more parasitic effects into account, up to the point that his ideal design will not function as originally planned.
Integrated Circuit Defect-Sensitivity: Theory and Computational Models
Author: Jose Pineda de Gyvez
Publisher: Springer
ISBN: 9780792393061
Category : Technology & Engineering
Languages : en
Pages : 167
Book Description
The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.
Publisher: Springer
ISBN: 9780792393061
Category : Technology & Engineering
Languages : en
Pages : 167
Book Description
The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the "silicon foundry" concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.
Génération de test de circuits intégrés fondée sur des modèles fonctionnels
Author: Margot Karam
Publisher:
ISBN:
Category :
Languages : fr
Pages : 338
Book Description
CETTE THESE CONCERNE L'UTILISATION DE MODELES FONCTIONNELS DANS LE TEST DE CIRCUITS INTEGRES COMPLEXES. DANS LA PREMIERE PARTIE, DES VECTEURS DE TEST SONT GENERES POUR LES AUTOMATES D'ETATS FINIS A PARTIR DE LEURS SPECIFICATIONS DE SYNTHESE. UN PREMIER ENSEMBLE DE VECTEURS DE TEST EST CALCULE EN PARCOURANT TOUS LES ARCS DU GRAPHE DE CONTROLE. LES VALEURS D'ENTREES NON SPECIFIEES SUR LES TRANSITIONS SONT FIXEES AFIN D'ACCROITRE LA COUVERTURE. IL EST MONTRE QUE CE TEST A UNE EXCELLENTE COUVERTURE PAR RAPPORT A SA LONGUEUR. LES FAUTES RESIDUELLES SONT DETECTEES PAR UNE METHODE DE DISTINCTION SUR LES MODELES MACHINE JUSTE MACHINE FAUSSE. LA DEUXIEME PARTIE EST CONSACREE AU TEST HIERARCHISE DE CIRCUITS COMPLEXES. LES VECTEURS DE TEST LOCAUX AUX BLOCS SONT JUSTIFIES VERS LES ENTREES PRIMAIRES ET PROPAGES EN AVANT VERS LES SORTIES PRIMAIRES EN UTILISANT DES VARIABLES SYMBOLIQUES ET DES MODELES FONCTIONNELS POUR LES BLOCS TRAVERSES. DES TECHNIQUES ORIGINALE DE PROPAGATION RETARDEE PERMETTENT DE RESTREINDRE LE NOMBRE D'ECHECS DES PROPAGATIONS. UN PROTOTYPE EN PROLOG A ETE EXPERIMENTE
Publisher:
ISBN:
Category :
Languages : fr
Pages : 338
Book Description
CETTE THESE CONCERNE L'UTILISATION DE MODELES FONCTIONNELS DANS LE TEST DE CIRCUITS INTEGRES COMPLEXES. DANS LA PREMIERE PARTIE, DES VECTEURS DE TEST SONT GENERES POUR LES AUTOMATES D'ETATS FINIS A PARTIR DE LEURS SPECIFICATIONS DE SYNTHESE. UN PREMIER ENSEMBLE DE VECTEURS DE TEST EST CALCULE EN PARCOURANT TOUS LES ARCS DU GRAPHE DE CONTROLE. LES VALEURS D'ENTREES NON SPECIFIEES SUR LES TRANSITIONS SONT FIXEES AFIN D'ACCROITRE LA COUVERTURE. IL EST MONTRE QUE CE TEST A UNE EXCELLENTE COUVERTURE PAR RAPPORT A SA LONGUEUR. LES FAUTES RESIDUELLES SONT DETECTEES PAR UNE METHODE DE DISTINCTION SUR LES MODELES MACHINE JUSTE MACHINE FAUSSE. LA DEUXIEME PARTIE EST CONSACREE AU TEST HIERARCHISE DE CIRCUITS COMPLEXES. LES VECTEURS DE TEST LOCAUX AUX BLOCS SONT JUSTIFIES VERS LES ENTREES PRIMAIRES ET PROPAGES EN AVANT VERS LES SORTIES PRIMAIRES EN UTILISANT DES VARIABLES SYMBOLIQUES ET DES MODELES FONCTIONNELS POUR LES BLOCS TRAVERSES. DES TECHNIQUES ORIGINALE DE PROPAGATION RETARDEE PERMETTENT DE RESTREINDRE LE NOMBRE D'ECHECS DES PROPAGATIONS. UN PROTOTYPE EN PROLOG A ETE EXPERIMENTE