Feasibility and Implementation Study of a High-throughput DVB-S2 LDPC Decoder on FPGA Architecture PDF Download
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Author: Etienne Boistault
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Languages : en
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[ENGLISH] The aim of this project consists in the study of the error correcting codes LDPC (Low Density Parity Check) in the context of the DVB-S2 standard (Digital Video Broadcasting for Satellite version 2) in order to design a functional high-throughput decoder running on a FPGA architecture. This system would be integrated to a High Data rate Receiver; a product manufactured by Zodiac Data Systems, a French aerospace company specialized in embedded systems. This project has been divided in four parts: the first one being a literature review of the LDPC codes, DVB-S2 standard and implementations ideas. The second phase was the development of a simulator in C/C++ using Microsoft Visual Studio 6.0. Thirdly, a study has been carried out in order to develop a design that will fit inside the system, following the constraints of the FPGA architecture. In parallel, changes have been made to the simulator for it to be as close as possible to the final design and obtain reference curves. Finally, the implementation of the decoder subsystem has been started in a FPGA using the Xilinx ISE program which works with VHDL language. This document is divided into four chapters, each one explaining a specific aspect of the project. The first chapter is an introduction to the LDPC codes, to the DVB-S2 standard and to the field-programmable gate array (FPGA). Chapter two is a comprehensive study of LDPC codes and an explained selection of development choices for the implementation of the decoding along with curves obtained thanks to early versions of the simulator. The third chapter provides the details of the adaptations of the design to fit in a FPGA environment. The last chapter is focused, on the development of the FPGA blocks to execute the decoding following the specifications.
Author: Etienne Boistault
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Languages : en
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[ENGLISH] The aim of this project consists in the study of the error correcting codes LDPC (Low Density Parity Check) in the context of the DVB-S2 standard (Digital Video Broadcasting for Satellite version 2) in order to design a functional high-throughput decoder running on a FPGA architecture. This system would be integrated to a High Data rate Receiver; a product manufactured by Zodiac Data Systems, a French aerospace company specialized in embedded systems. This project has been divided in four parts: the first one being a literature review of the LDPC codes, DVB-S2 standard and implementations ideas. The second phase was the development of a simulator in C/C++ using Microsoft Visual Studio 6.0. Thirdly, a study has been carried out in order to develop a design that will fit inside the system, following the constraints of the FPGA architecture. In parallel, changes have been made to the simulator for it to be as close as possible to the final design and obtain reference curves. Finally, the implementation of the decoder subsystem has been started in a FPGA using the Xilinx ISE program which works with VHDL language. This document is divided into four chapters, each one explaining a specific aspect of the project. The first chapter is an introduction to the LDPC codes, to the DVB-S2 standard and to the field-programmable gate array (FPGA). Chapter two is a comprehensive study of LDPC codes and an explained selection of development choices for the implementation of the decoding along with curves obtained thanks to early versions of the simulator. The third chapter provides the details of the adaptations of the design to fit in a FPGA environment. The last chapter is focused, on the development of the FPGA blocks to execute the decoding following the specifications.
Author: Kai Zhang
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Languages : en
Pages : 244
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Abstract: The Low-Density Parity-Check (LDPC) codes, which were invented by Gallager back in 1960s, have attracted considerable attentions recently. Compared with other error correction codes, LDPC codes are well suited for wireless, optical, and magnetic recording systems due to their near- Shannon-limit error-correcting capacity, high intrinsic parallelism and high-throughput potentials. With these remarkable characteristics, LDPC codes have been adopted in several recent communication standards such as 802.11n (Wi-Fi), 802.16e (WiMax), 802.15.3c (WPAN), DVB-S2 and CMMB. This dissertation is devoted to exploring efficient VLSI architectures for high-performance LDPC decoders and LDPC-like detectors in sparse inter-symbol interference (ISI) channels. The performance of an LDPC decoder is mainly evaluated by area efficiency, error-correcting capability, throughput and rate flexibility. With this work we investigate tradeoffs between the four performance aspects and develop several decoder architectures to improve one or several performance aspects while maintaining acceptable values for other aspects ... Layered decoding algorithm, which is popular in LDPC decoding, is also adopted in this paper. Simulation results show that the layered decoding doubles the convergence speed of the iterative belief propagation process. Exploring the special structure of the connections between the check nodes and the variable nodes on the factor graph, we propose an effective detector architecture for generic sparse ISI channels to facilitate the practical application of the proposed detection algorithm. The proposed architecture is also reconfigurable in order to switch flexible connections on the factor graph in the time-varying ISI channels.
Author: Lan Yang
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Languages : en
Pages : 52
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Due to its near Shannon limit performance in high speed communication, low-density parity check (LDPC) code has performed a strong comeback recent years. In this work, a partial parallel decoding architecture is proposed based on a column-layered LDPC decoding scheme [2]. The purpose of this work is to make a tradeoff between area cost and throughput. I construct the structure of the partial parallel decoder, and compare its throughput and area cost with the design in [2]. Then I obtain the synthesis results of my design with Xilinx FPGA tool. The device utilization summary and timing summary are provided at the end of this work. Comparing with the design in [2], the partial parallel design in my work needs much less hardware resources. As a result, when the area is limit and a lower throughput is acceptable, my design can be considered instead of the design in [2].
Author: Engling Yeo
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Languages : en
Pages : 372
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Author: Manpreet Singh
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Languages : en
Pages : 73
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Low-density parity-check (LDPC) codes are a class of easily decodable error-correcting codes. Published parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on Field-Programmable Gate Array (FPGA) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a digit-online decoder depends on various factors, like input log-likelihood ratio (LLR) bit precision, signal-to-noise ratio (SNR) and maximum number of iterations. The design is implemented on an Altera Stratix IV GX EP4SGX230 FPGA, which comes on an Altera DE4 Development and Education Board. In this work, both parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit, rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a random-data generator, WiMAX Encoder, shift-out register, additive white Gaussian noise (AWGN) generator, channel LLR buffer, WiMAX Decoder and bit-error rate (BER) Calculator. The random-data generator outputs pseudo-random bit patterns through an implemented linear-feedback shift register (LFSR). Digit-online decoders with input LLR precisions ranging from 6 to 13 bits and parallel decoders with input LLR precisions ranging from 3 to 6 bits are synthesized in a Stratix IV FPGA. The digit-online decoders can be clocked at higher frequency for higher LLR precisions. A digit-online decoder can be used to decode two frames simultaneously in frame-interlaced mode. For the 6-bit implementation of digit-online decoder in single-frame mode, the minimum throughput achieved is 740 Mb/s at low SNRs. For the case of 11-bit LLR digit-online decoder in frame-interlaced mode, the minimum throughput achieved is 1363 Mb/s. Detailed analysis such as effect of SNR and LLR precision on decoder power is presented. Also, the effect of changing LLR precision on max clock frequency and logic utilization on the parallel and the digit-online decoders is studied. Alongside, power per iteration for a 6-bit LLR input digit-online decoder is also reported.
Author: Weihuang Wang
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Languages : en
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This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels and general AWGN channels. A model of a memory-efficient low-power high-throughput multi-rate array LDPC decoder as well as its FPGA implementation results is first presented. Then, I propose a decoding scheme that provides the feature of constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It pre-analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. This is in contrast to the conventional fixed-iteration decoding schemes that operate at a fixed voltage level regardless of the quality of data received. Analysis shows that the proposed decoding scheme is widely applicable for both two-phase message-passing (TPMP) decoding algorithm and turbo decoding message passing (TDMP) decoding algorithm in block fading channels, and it is independent of the specific LDPC decoder architecture. A decoder architecture utilizing our recently published multi-rate decoding architecture for general AWGN channels is also presented. The result of this thesis is a decoder design scheme that provides a judicious trade-off between power consumption and coding gain.
Author: Xiaoheng Chen
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ISBN: 9781124906669
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Languages : en
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Since the rediscovery of low-density parity-check (LDPC) codes in the late 1990s, tremendous progress has been made in code construction and design, decoding algorithms, and decoder implementation of these capacity-approaching codes. Recently, LDPC codes are considered for applications such as high-speed satellite and optical communications, the hard disk drives, and high-density flash memory based storage systems, which require that the codes are free of error-floor down to bit error rate (BER) as low as 10−12 to 10−15. FPGAs are usually used to evaluate the error performance of codes, since one can exploit the finite word length and extremely high internal memory bandwidth of an FPGA. Existing FPGA-based LDPC decoders fail to utilize the configurability and read-first mode of embedded memory in the FPGAs, and thus result in limited throughput and codes sizes. Four optimization techniques, i.e., vectorization, folding, message relocation, and circulant permutation matrix (CPM) sharing, are proposed to improve the throughput, scalability, and efficiency of FPGA-based decoders. Also, a semi-automatic CAD tool called QCSYN (Quasi-Cyclic LDPC decoder SYNthesis) is designed to shorten the implementation time of decoders. Using the above techniques, a high-rate (16129,15372) code is shown to have no error-floor down to the BER of 10−14. Also, it is very difficult to construct codes that do not exhibit an error floor down to 10−15 or so. Without detailed knowledge of dominant trapping sets, a backtracking-based reconfigurable decoder is designed to lower the error floor of a family of structurally compatible quasi-cyclic LDPC codes by one to two orders of magnitudes. Hardware reconfigurability is another significant feature of LDPC decoders. A tri-mode decoder for the (4095,3367) Euclidean geometry code is designed to work with three compatible binary message passing decoding algorithms. Note that this code contains 262080 edges (21.3 times of the (2048,1723) 10GBASE-T code) in its Tanner graph and is the largest code ever implemented. Besides, an efficient QC-LDPC Shift Network (QSN) is proposed to reduce the interconnect delay and control logic of circular shift network, a core component in the reconfigurable decoder that supports a family of structurally compatible codes. The interconnect delay and control logic area are reduced by a factor of 2.12 and 8, respectively. Non-binary LDPC codes are effective in combating burst errors. Using the power representation of the elements in the Galois field to organize both intrinsic and extrinsic messages, we present an efficient decoder architecture for non-binary QC-LDPC codes. The proposed decoder is reconfigurable and can be used to decode any code of a given field size. The decoder supports both regular and irregular non-binary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.
Author: Yuta Toriyama
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Languages : en
Pages : 133
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Binary Low-Density Parity-Check (LDPC) codes are a type of error correction code known to exhibit excellent error-correcting capabilities, and have increasingly been applied as the forward error correction solution in a multitude of systems and standards, such as wireless communications, wireline communications, and data storage systems. In the pursuit of codes with even higher coding gain, non-binary LDPC (NB-LDPC) codes defined over a Galois field of order q have risen as a strong replacement candidate. For codes defined with similar rate and length, NB-LDPC codes exhibit a significant coding gain improvement relative to that of their binary counterparts. Unfortunately, NB-LDPC codes are currently limited from practical application by the immense complexity of their decoding algorithms, because the improved error-rate performance of higher field orders comes at the cost of increasing decoding algorithm complexity. Currently available ASIC implementation solutions for NB-LDPC code decoders are simultaneously low in throughput and power-hungry, leading to a low energy efficiency. We propose several techniques at the algorithm level as well as hardware architecture level in an attempt to bring NB-LDPC codes closer to practical deployment. On the algorithm side, we propose several algorithmic modifications and analyze the corresponding hardware cost alleviation as well as impact on coding gain. We also study the quantization scheme for NB-LDPC decoders, again in the context of both the hardware and coding gain impacts, and we propose a technique that enables a good tradeoff in this space. On the hardware side, we develop a FPGA-based NB-LDPC decoder platform for architecture prototyping as well as hardware acceleration of code evaluation via error rate simulations. We also discuss the architectural techniques and innovations corresponding to our proposed algorithm for optimization of the implementation. Finally, a proof-of-concept ASIC chip is realized that integrates many of the proposed techniques. We are able to achieve a 3.7x improvement in the information throughput and 23.8x improvement in the energy efficiency over prior state-of-the-art, without sacrificing the strong error correcting capabilities of the NB-LDPC code.
Author: Massoud Khajeh
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Languages : en
Pages : 0
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In spite of their powerful error correcting capability, Low Density Parity Check codes (LDPC) have been ignored due to their high complexity. Around three decades after the invention of this code, researchers returned back their attention to it and tried to make some significant improvements in complexity. As the result, the LDPC codes were widely considered in the next generation error correcting codes in telecommunication systems. In 2005, the new standard for Digital Video Broadcasting (DVB-S2) used LDPC codes as its channel coding scheme. The features of the above mentioned code allow a transmission near the Shannon limit. In this thesis, we first review the LDPC codes in general, and then we present the encoding and decoding scheme which is used in the DVB-S2 standard. We discuss regular and irregular LDPC codes and compare the advantages and disadvantages of these codes with each other. In this thesis, we consider a higher block length for the LDPC code compared to DVB-S2 standard to improve the performance. We propose an efficient hybrid parity check matrix for this code. This parity check matrix has the same number of base addresses as the case for DVB-S2 which processes high block length with the same complexity. At the end, simulation results are provided to show the improvement in the performance.
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Languages : en
Pages : 0
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