Fast and Accurate Lithography Simulation and Optical Proximity Correction for Nanometer Design for Manufacturing PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Fast and Accurate Lithography Simulation and Optical Proximity Correction for Nanometer Design for Manufacturing PDF full book. Access full book title Fast and Accurate Lithography Simulation and Optical Proximity Correction for Nanometer Design for Manufacturing by . Download full books in PDF and EPUB format.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 364
Get Book Here
Book Description
As semiconductor manufacture feature sizes scale into the nanometer dimension, circuit layout printability is significantly reduced due to the fundamental limit of lithography systems. This dissertation studies related research topics in lithography simulation and optical proximity correction. A recursive integration method is used to reduce the errors in transmission cross coefficient (TCC), which is an important factor in the Hopkins Equation in aerial image simulation. The runtime is further reduced, without increasing the errors, by using the fact that TCC is usually computed on uniform grids. A flexible software framework, ELIAS, is also provided, which can be used to compute TCC for various lithography settings, such as different illuminations. Optimal coherent approximations (OCAs), which are used for full-chip image simulation, can be speeded up by considering the symmetric properties of lithography systems. The runtime improvement can be doubled without loss of accuracy. This improvement is applicable to vectorial imaging models as well. Even in the case where the symmetric properties do not hold strictly, the new method can be generalized such that it could still be faster than the old method. Besides new numerical image simulation algorithms, variations in lithography systems are also modeled. A Variational LIthography Model (VLIM) as well as its calibration method are provided. The Variational Edge Placement Error (V-EPE) metrics, which is an improvement of the original Edge Placement Error (EPE) metrics, is introduced based on the model. A true process-variation aware OPC (PV-OPC) framework is proposed using the V-EPE metric. Due to the analytical nature of VLIM, our PV-OPC is only about 2-3x slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. The EPE metrics have been used in conventional OPC algorithms, but it requires many intensity simulations and takes the majority of the OPC runtime. By making the OPC algorithm intensity based (IB-OPC) rather than EPE based, we can reduce the number of intensity simulations and hence reduce the OPC runtime. An efficient intensity derivative computation method is also provided, which makes the new algorithm converge faster than the EPE based algorithm. Our experimental results show a runtime speedup of more than 10x with comparable result quality compared to the EPE based OPC. The above mentioned OPC algorithms are vector based. Other categories of OPC algorithms are pixel based. Vector based algorithms in general generate less complex masks than those of pixel based ones. But pixel based algorithms produce much better results than vector based ones in terms of contour fidelity. Observing that vector based algorithms preserve mask shape topologies, which leads to lower mask complexities, we combine the strengths of both categories--the topology invariant property and the pixel based mask representation. A topological invariant pixel based OPC (TIP-OPC) algorithm is proposed, with lithography friendly mask topological invariant operations and an efficient Fast Fourier Transform (FFT) based cost function sensitivity computation. The experimental results show that TIP-OPC can achieve much better post-OPC contours compared with vector based OPC while maintaining the mask shape topologies.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 364
Get Book Here
Book Description
As semiconductor manufacture feature sizes scale into the nanometer dimension, circuit layout printability is significantly reduced due to the fundamental limit of lithography systems. This dissertation studies related research topics in lithography simulation and optical proximity correction. A recursive integration method is used to reduce the errors in transmission cross coefficient (TCC), which is an important factor in the Hopkins Equation in aerial image simulation. The runtime is further reduced, without increasing the errors, by using the fact that TCC is usually computed on uniform grids. A flexible software framework, ELIAS, is also provided, which can be used to compute TCC for various lithography settings, such as different illuminations. Optimal coherent approximations (OCAs), which are used for full-chip image simulation, can be speeded up by considering the symmetric properties of lithography systems. The runtime improvement can be doubled without loss of accuracy. This improvement is applicable to vectorial imaging models as well. Even in the case where the symmetric properties do not hold strictly, the new method can be generalized such that it could still be faster than the old method. Besides new numerical image simulation algorithms, variations in lithography systems are also modeled. A Variational LIthography Model (VLIM) as well as its calibration method are provided. The Variational Edge Placement Error (V-EPE) metrics, which is an improvement of the original Edge Placement Error (EPE) metrics, is introduced based on the model. A true process-variation aware OPC (PV-OPC) framework is proposed using the V-EPE metric. Due to the analytical nature of VLIM, our PV-OPC is only about 2-3x slower than the conventional OPC, but it explicitly considers the two main sources of process variations (exposure dose and focus variations) during OPC. The EPE metrics have been used in conventional OPC algorithms, but it requires many intensity simulations and takes the majority of the OPC runtime. By making the OPC algorithm intensity based (IB-OPC) rather than EPE based, we can reduce the number of intensity simulations and hence reduce the OPC runtime. An efficient intensity derivative computation method is also provided, which makes the new algorithm converge faster than the EPE based algorithm. Our experimental results show a runtime speedup of more than 10x with comparable result quality compared to the EPE based OPC. The above mentioned OPC algorithms are vector based. Other categories of OPC algorithms are pixel based. Vector based algorithms in general generate less complex masks than those of pixel based ones. But pixel based algorithms produce much better results than vector based ones in terms of contour fidelity. Observing that vector based algorithms preserve mask shape topologies, which leads to lower mask complexities, we combine the strengths of both categories--the topology invariant property and the pixel based mask representation. A topological invariant pixel based OPC (TIP-OPC) algorithm is proposed, with lithography friendly mask topological invariant operations and an efficient Fast Fourier Transform (FFT) based cost function sensitivity computation. The experimental results show that TIP-OPC can achieve much better post-OPC contours compared with vector based OPC while maintaining the mask shape topologies.
Author: Nicolas Bailey Cobb
Publisher:
ISBN:
Category :
Languages : en
Pages : 286
Get Book Here
Book Description
Author: Chul-Hong Park
Publisher:
ISBN:
Category :
Languages : en
Pages : 202
Get Book Here
Book Description
Photolithography has been a key enabler of the aggressive IC technology scaling implicit in Moore's Law. As minimum feature sizes approach the physical limits of lithography and the manufacturing process, resolution enhancement techniques (RETs) dictate certain tradeoffs with various aspects of process and performance. This in turn has led to unpredictable design, unpredictable manufacturing, and low yield. As a result, close communication between designer and manufacturer has become essential to overcome the uncertainties of design and manufacturing. The design for manufacturability (DFM) paradigm has emerged recently to improve communications at the design-manufacturing interface and to reduce manufacturing variability. DFM is a set of technologies and methodologies that both help the designer extract maximum value from silicon process technology and solve "unsolvable" manufacturing challenges. Traditional DFM techniques, which include design rule check (DRC) and optical proximity correction (OPC), have been successfully used until now. However, as the extent and complexity of lithography variations increase, traditional techniques are no longer adequate to accommodate the various lithography demands. This thesis focuses on ways to mitigate the impact of lithography variations on design by establishing new interfaces between design and manufacturing. The motivations for doing so are improved printability, timing and leakage as well as reduced design cost. To improve printability, we propose a detailed placement perturbation technique for improved depth of focus and process window. Using a dynamic programming (DP)-based method for the perturbation, the technique facilitates insertion of scattering bars and etch dummy features, reducing inter-cell forbidden pitches almost completely. We also propose a novel auxiliary pattern-enabled cell-based OPC which can improve the edge placement error over cell-based OPC. The technique improves runtime which has grown unacceptably in model-based OPC, while retaining its runtime advantage as well as timing and leakage optimization. The detailed placement framework is also available to allow opportunistic insertion of auxiliary pattern around cell instances in the design layout. Aberration leads to linewidth variation which is fundamental to achieve timing performance and manufacturing yield. We describe an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven global placement technique which utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. The use of the technique along with field blading achieves significant cycle time improvement. DoseMapper technique adopted in advanced lithography equipments has been used to reduce the across-chip linewidth variation. We propose a novel method to enhance timing yield as well as reduce leakage power by combined dose map and placement optimizations. The new dose map is not determined to have the same critical dimension (CD) in all transistor gates, but optimized to have different linewidths. That is, for devices on setup timing-critical paths, a smaller than nominal CD will be desirable, since this creates a faster-switching transistor. On the other hand, for devices on hold timing-critical paths, a larger than nominal gate CD will be desirable since this creates a less leaky transistor. Last, the golden verification signoff tool using simulation-based approach represents a runtime-quality tradeoff that is high in quality, but also high in runtime. We are motivated to develop a low-runtime pre-filter that reduces the amount of layout area to be analyzed by the golden tool, without compromising the overall quality finding hotspots. We demonstrate a dual graph-based hotspot filtering technique that enables fast and accurate estimation.
Author: Xu Ma
Publisher: Wiley
ISBN: 9780470596975
Category : Technology & Engineering
Languages : en
Pages : 226
Get Book Here
Book Description
A Unified Summary of the Models and Optimization Methods Used in Computational Lithography Optical lithography is one of the most challenging areas of current integrated circuit manufacturing technology. The semiconductor industry is relying more on resolution enhancement techniques (RETs), since their implementation does not require significant changes in fabrication infrastructure. Computational Lithography is the first book to address the computational optimization of RETs in optical lithography, providing an in-depth discussion of optimal optical proximity correction (OPC), phase shifting mask (PSM), and off-axis illumination (OAI) RET tools that use model-based mathematical optimization approaches. The book starts with an introduction to optical lithography systems, electric magnetic field principles, and the fundamentals of optimization from a mathematical point of view. It goes on to describe in detail different types of optimization algorithms to implement RETs. Most of the algorithms developed are based on the application of the OPC, PSM, and OAI approaches and their combinations. Algorithms for coherent illumination as well as partially coherent illumination systems are described, and numerous simulations are offered to illustrate the effectiveness of the algorithms. In addition, mathematical derivations of all optimization frameworks are presented. The accompanying MATLAB® software files for all the RET methods described in the book make it easy for readers to run and investigate the codes in order to understand and apply the optimization algorithms, as well as to design a set of optimal lithography masks. The codes may also be used by readers for their research and development activities in their academic or industrial organizations. An accompanying MATLAB® software guide is also included. An accompanying MATLAB® software guide is included, and readers can download the software to use with the guide at ftp://ftp.wiley.com/public/sci_tech_med/computational_lithography. Tailored for both entry-level and experienced readers, Computational Lithography is meant for faculty, graduate students, and researchers, as well as scientists and engineers in industrial organizations whose research or career field is semiconductor IC fabrication, optical lithography, and RETs. Computational lithography draws from the rich theory of inverse problems, optics, optimization, and computational imaging; as such, the book is also directed to researchers and practitioners in these fields.
Author:
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 442
Get Book Here
Book Description
Author: Lokesh Subramany
Publisher:
ISBN:
Category : Lithography
Languages : en
Pages : 62
Get Book Here
Book Description
Optical Proximity Correction (OPC) is a part of a family of techniques called Resolution Enhancement Techniques (RET). These techniques are employed to increase the resolution of a lithography system and improve the quality of the printed pattern. The fidelity of the pattern is degraded due to the disparity between the wavelength of light used in optical lithography, and the required size of printed features. In order to improve the aerial image, the mask is modified. This process is called OPC, OPC is an iterative process where a mask shape is modified to decrease the disparity between the required and printed shapes. After each modification the chip is simulated again to quantify the effect of the change in the mask. Thus, lithography simulation is an integral part of OPC and a fast lithography simulator will definitely decrease the time required to perform OPC on an entire chip. A lithography simulator which uses wavelets to compute the aerial image has previously been developed. In this thesis I extensively modify this simulator in order to execute it on a Graphics Processing Unit (GPU). This leads to a lithography simulator that is considerably faster than other lithography simulators and when used in OPC will lead to drastically decreased runtimes. The other work presented in the proposal is a fast OPC tool which allows us to perform OPC on circuits faster than other tools. We further focus our attention on metrics like runtime, edge placement error and shot size and present schemes to improve these metrics.
Author: Seongbo Shim
Publisher: Springer
ISBN: 331976294X
Category : Technology & Engineering
Languages : en
Pages : 144
Get Book Here
Book Description
This book discusses physical design and mask synthesis of directed self-assembly lithography (DSAL). It covers the basic background of DSAL technology, physical design optimizations such as placement and redundant via insertion, and DSAL mask synthesis as well as its verification. Directed self-assembly lithography (DSAL) is a highly promising patterning solution in sub-7nm technology.
Author: Ahmed Awad
Publisher:
ISBN:
Category : Technology
Languages : en
Pages :
Get Book Here
Book Description
As advanced technology nodes continue scaling down into sub-16 nm regime, optical microlithography becomes more vulnerable to process variations. As a result, overall lithographic yield continuously degrades. Since next-generation lithography (NGL) is still not mature enough, the industry relies heavily on resolution enhancement techniques (RETs), wherein optical proximity correction (OPC) with 193 nm immersion lithography is dominant in the foreseeable future. However, OPC algorithms are getting more aggressive. Consequently, complex mask solutions are outputted. Furthermore, this results in long computation time along with mask data volume explosion. In this chapter, recent state-of-the-art OPC algorithms are discussed. Thereafter, the performance of a recently published fast OPC methodology-to generate highly manufactured mask solutions with acceptable pattern fidelity under process variations-is verified on the public benchmarks.
Author: Ibrahim (Abe) M. Elfadel
Publisher: Springer
ISBN: 3030046664
Category : Technology & Engineering
Languages : en
Pages : 694
Get Book Here
Book Description
This book provides readers with an up-to-date account of the use of machine learning frameworks, methodologies, algorithms and techniques in the context of computer-aided design (CAD) for very-large-scale integrated circuits (VLSI). Coverage includes the various machine learning methods used in lithography, physical design, yield prediction, post-silicon performance analysis, reliability and failure analysis, power and thermal analysis, analog design, logic synthesis, verification, and neuromorphic design. Provides up-to-date information on machine learning in VLSI CAD for device modeling, layout verifications, yield prediction, post-silicon validation, and reliability; Discusses the use of machine learning techniques in the context of analog and digital synthesis; Demonstrates how to formulate VLSI CAD objectives as machine learning problems and provides a comprehensive treatment of their efficient solutions; Discusses the tradeoff between the cost of collecting data and prediction accuracy and provides a methodology for using prior data to reduce cost of data collection in the design, testing and validation of both analog and digital VLSI designs. From the Foreword As the semiconductor industry embraces the rising swell of cognitive systems and edge intelligence, this book could serve as a harbinger and example of the osmosis that will exist between our cognitive structures and methods, on the one hand, and the hardware architectures and technologies that will support them, on the other....As we transition from the computing era to the cognitive one, it behooves us to remember the success story of VLSI CAD and to earnestly seek the help of the invisible hand so that our future cognitive systems are used to design more powerful cognitive systems. This book is very much aligned with this on-going transition from computing to cognition, and it is with deep pleasure that I recommend it to all those who are actively engaged in this exciting transformation. Dr. Ruchir Puri, IBM Fellow, IBM Watson CTO & Chief Architect, IBM T. J. Watson Research Center
Author: David Huang
Publisher: The Electrochemical Society
ISBN: 1566777038
Category : Science
Languages : en
Pages : 1124
Get Book Here
Book Description
ISTC/CSTIC is an annual semiconductor technology conference covering all the aspects of semiconductor technology and manufacturing, including devices, design, lithography, integration, materials, processes, manufacturing as well as emerging semiconductor technologies and silicon material applications. ISTC/CSTIC 2009 was merged by ISTC (International Semiconductor Technology Conference) and CSTIC (China Semiconductor Technology International Conference), the two industry leading technical conferences in China, and consisted of one plenary session and nine technical symposia. This issue of ECS Transactions contains 159 papers from the conference.
