Efficient Generation of Test Patterns Using Boolean Satisfiability PDF Download
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Author: Tracy Larrabee
Publisher:
ISBN:
Category : Algebra, Boolean
Languages : en
Pages : 57
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Book Description
Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks."
Author: Tracy Larrabee
Publisher:
ISBN:
Category : Algebra, Boolean
Languages : en
Pages : 57
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Book Description
Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the addition of any heuristic used by the structural search methods. The Boolean satisfiability method has produced excellent results on popular test pattern generation benchmarks."
Author: Stephan Eggersglüß
Publisher: Springer Science & Business Media
ISBN: 1441999760
Category : Technology & Engineering
Languages : en
Pages : 208
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Book Description
This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.
Author: Digital Equipment Corporation. Western Research Laboratory
Publisher:
ISBN:
Category : Electronic circuits
Languages : en
Pages :
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Book Description
The first paper, Efficient Generation of Test Patterns Using Boolean Difference, gives an overview of a successful test pattern generation system using the Boolean satisfiability method. The second paper, A Framework for Evaluating Test Pattern Generation Strategies, describes potential test pattern generation heuristics and their efficacy in the Boolean satisfiability system."
Author: Rolf Drechsler
Publisher: Springer Science & Business Media
ISBN: 9048123607
Category : Technology & Engineering
Languages : en
Pages : 196
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Book Description
In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.
Author: Stephan Eggersglüß
Publisher:
ISBN:
Category :
Languages : en
Pages : 182
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Book Description
Author: N. K. Jha
Publisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022
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Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Author: A. Biere
Publisher: IOS Press
ISBN: 1643681613
Category : Computers
Languages : en
Pages : 1486
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Book Description
Propositional logic has been recognized throughout the centuries as one of the cornerstones of reasoning in philosophy and mathematics. Over time, its formalization into Boolean algebra was accompanied by the recognition that a wide range of combinatorial problems can be expressed as propositional satisfiability (SAT) problems. Because of this dual role, SAT developed into a mature, multi-faceted scientific discipline, and from the earliest days of computing a search was underway to discover how to solve SAT problems in an automated fashion. This book, the Handbook of Satisfiability, is the second, updated and revised edition of the book first published in 2009 under the same name. The handbook aims to capture the full breadth and depth of SAT and to bring together significant progress and advances in automated solving. Topics covered span practical and theoretical research on SAT and its applications and include search algorithms, heuristics, analysis of algorithms, hard instances, randomized formulae, problem encodings, industrial applications, solvers, simplifiers, tools, case studies and empirical results. SAT is interpreted in a broad sense, so as well as propositional satisfiability, there are chapters covering the domain of quantified Boolean formulae (QBF), constraints programming techniques (CSP) for word-level problems and their propositional encoding, and satisfiability modulo theories (SMT). An extensive bibliography completes each chapter. This second edition of the handbook will be of interest to researchers, graduate students, final-year undergraduates, and practitioners using or contributing to SAT, and will provide both an inspiration and a rich resource for their work. Edmund Clarke, 2007 ACM Turing Award Recipient: "SAT solving is a key technology for 21st century computer science." Donald Knuth, 1974 ACM Turing Award Recipient: "SAT is evidently a killer app, because it is key to the solution of so many other problems." Stephen Cook, 1982 ACM Turing Award Recipient: "The SAT problem is at the core of arguably the most fundamental question in computer science: What makes a problem hard?"
Author: Abhijit Ghosh
Publisher: Springer Science & Business Media
ISBN: 1461536464
Category : Technology & Engineering
Languages : en
Pages : 224
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Book Description
In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance.
Author: Xinghao Chen
Publisher: Springer Science & Business Media
ISBN: 1461313295
Category : Technology & Engineering
Languages : en
Pages : 151
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Book Description
Branch-and-bound search has been known for a long time and has been widely used in solving a variety of problems in computer-aided design (CAD) and many important optimization problems. In many applications, the classic branch-and-bound search methods perform duplications of computations, or rely on the search decision trees which keep track of the branch-and-bound search processes. In CAD and many other technical fields, the computational cost of constructing branch-and-bound search decision trees in solving large scale problems is prohibitive and duplications of computations are intolerable. Efficient branch-and-bound methods are needed to deal with today's computational challenges. Efficient branch-and-bound methods must not duplicate computations. Efficient Branch and Bound Search with Application to Computer-Aided Design describes an efficient branch-and-bound method for logic justification, which is fundamental to automatic test pattern generation (ATPG), redundancy identification, logic synthesis, minimization, verification, and other problems in CAD. The method is called justification equivalence, based on the observation that justification processes may share identical subsequent search decision sequences. With justification equivalence, duplication of computations is avoided in the dynamic branch-and-bound search process without using search decision trees. Efficient Branch and Bound Search with Application to Computer-Aided Design consists of two parts. The first part, containing the first three chapters, provides the theoretical work. The second part deals with applications, particularly ATPG for sequential circuits. This book is particularly useful to readers who are interested in the design and test of digital circuits.
Author: Andreas Kuehlmann
Publisher: Springer Science & Business Media
ISBN: 1461502926
Category : Computers
Languages : en
Pages : 699
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Book Description
In 2002, the International Conference on Computer Aided Design (ICCAD) celebrates its 20th anniversary. This book commemorates contributions made by ICCAD to the broad field of design automation during that time. The foundation of ICCAD in 1982 coincided with the growth of Large Scale Integration. The sharply increased functionality of board-level circuits led to a major demand for more powerful Electronic Design Automation (EDA) tools. At the same time, LSI grew quickly and advanced circuit integration became widely avail able. This, in turn, required new tools, using sophisticated modeling, analysis and optimization algorithms in order to manage the evermore complex design processes. Not surprisingly, during the same period, a number of start-up com panies began to commercialize EDA solutions, complementing various existing in-house efforts. The overall increased interest in Design Automation (DA) re quired a new forum for the emerging community of EDA professionals; one which would be focused on the publication of high-quality research results and provide a structure for the exchange of ideas on a broad scale. Many of the original ICCAD volunteers were also members of CANDE (Computer-Aided Network Design), a workshop of the IEEE Circuits and Sys tem Society. In fact, it was at a CANDE workshop that Bill McCalla suggested the creation of a conference for the EDA professional. (Bill later developed the name).
