Author: Paul Mark Hansen
Publisher:
ISBN:
Category : Evaluation
Languages : en
Pages : 640
Get Book Here
Book Description
The hardware resources available on a single chip to implement VLSI CPU remain scarce, despite rapid technological advances. Reduced Instruction Set Computers (RISCs) reduce complexity and use the chip hardware resources to make the most frequently occurring operations fast. In this dissertation, the RISC philosophy is extended to specialized devices called coprocessors. Coprocessors increase system performance by reducing the number of instructions per program and the number of effective cycles per instruction. A method for evaluating coprocessor performance is developed, including a model that accounts for system, software, and hardware effects. Coprocessor implementations are characterized in terms of effectiveness and utilization by considering operation and overhead time for typical computations. Performance and interface characteristics of the SPUR floating-point coprocessor implementaion of the IEEE Standard are presented and compared to two popular commercial versions by Intel and Motorola. The SPUR FPU is a factor of three to 50 times faster than the commercial versions for comparable technology and clock rates. For each architecture, the influence on performance of each of the following is identified: the bus width between the floating- point unit and operand storage, the operand transfer protocols implemented in hardware, the concurrent execution model, the speed of the function units, the floating-point instruction semantics, and the data cache service time. Execution time spent in overhead is shown to increase to more than 90% for some architectures if equipped with faster floating-point units. This suggests that coprocessor interface architectures must change dramatically to keep pace with the rapid advance in CPU execution rates to be effective. The combinatorial optimization problem of finding the shortest path between two vertices in a directed graph is presented. Algorithms for scan-based relaxation techniques and Dijkstra's shortest-path algorithm are considered in detail. A path optimization coprocessor based on the SPUR model is proposed that achieves nearly three orders of magnitude improvement in performance over software implementations, and two to three orders of magnitude improvement in cost with performance comparable to dedicated hardware devices or specialized and multi-computer architectures. Finally, the SPUR coprocessor architecture is evaluated for three other applications: digital signal processing, vector floating-floating arithmetic, and support for Prolog language.
Author: P. Antognetti
Publisher: Springer Science & Business Media
ISBN: 9400951434
Category : Technology & Engineering
Languages : en
Pages : 289
Get Book Here
Book Description
Proceedings of the NATO Advanced Study Institute, SOGESTA, Urbino, Italy, July 9-20, 1984
Author: S.B. Furber
Publisher: Routledge
ISBN: 1351405373
Category : Technology & Engineering
Languages : en
Pages : 398
Get Book Here
Book Description
With the expectation that architectural improvements will play a significant role inadvancing processor performance, it is critical for readers to maintain an up-to-date,unified overview of technological advances in this vital research area.Gathering into one place material that had been scattered throughout the literaturemakingit difficult to obtain detailed information on computer designs-this importantbook describes the main architectural and organizational features of modem mini- andmicrocomputers. In addition, it explains the RISC philosophy by supplying historicalbackground information and excellent examples of several commercially available RISCmicroprocessors.Limiting attention to VLSI implementations of RISC processors, VLSI RISCArchitecture and Organization offers insight into design issues that arose indeveloping a RISC system, using the VLSI RISC chip set developed at AcornComputers Limited as an example ... discusses options considered during the designprocess, the basis for the decisions made, and implementation details . . . describescontemporary RISC architecture, comparing and contrasting different designs ... andlooks at future trends in RISC research.Discussing the topic cohesively and comprehensively-from initial study into reducedinstructions sets to the widespread introduction of RISC architectures into mainstreamcomputer products-VLSI RISC Architecture and Organization is aninvaluable reference for electrical, electronics, and computer engineers; computerarchitects and scientists; hardware systems designers; and upper-level undergraduate andgraduate students in computer science and electrical engineering courses.
Author: Ravi Shankar
Publisher: Academic Press
ISBN: 1483217841
Category : Technology & Engineering
Languages : en
Pages : 502
Get Book Here
Book Description
VLSI Electronics Microstructure Science, Volume 20: VLSI and Computer Architecture reviews the approaches in design principles and techniques and the architecture for computer systems implemented in VLSI. This volume is divided into two parts. The first section is concerned with system design. Chapters under this section focus on the discussion of such topics as the evolution of VLSI; system performance and processor design considerations; and VLSI system design and processing tools. Part II of the book focuses on the architectural possibilities that have become cost effective with the development of VLSI circuits. Topics on architectural requirements and various architectures such as the Reduced Instruction Set, Extended Von Neumann, Language-Oriented, and Microprogrammable architectures are elaborated in detail. Also included are chapters that discuss the evaluation of architecture, multiprocessing configurations, and the future of VLSI. Computer designers, those evaluating computer systems, researchers, and students of computer architecture will find the book very useful.
Author: Manolis G. H. Katevenis
Publisher: MIT Press (MA)
ISBN:
Category : Computers
Languages : en
Pages : 242
Get Book Here
Book Description
This book demonstrates the practicality of the RISC approach.
Author: S. B. Furber
Publisher: CRC Press
ISBN: 9780824781514
Category : Technology & Engineering
Languages : en
Pages : 398
Get Book Here
Book Description
With the expectation that architectural improvements will play a significant role inadvancing processor performance, it is critical for readers to maintain an up-to-date, unified overview of technological advances in this vital research area.Gathering into one place material that had been scattered throughout the literaturemakingit difficult to obtain detailed information on computer designs-this importantbook describes the main architectural and organizational features of modem mini- andmicrocomputers. In addition, it explains the RISC philosophy by supplying historicalbackground information and excellent examples of several commercially available RISCmicroprocessors.Limiting attention to VLSI implementations of RISC processors, VLSI RISCArchitecture and Organization offers insight into design issues that arose indeveloping a RISC system, using the VLSI RISC chip set developed at AcornComputers Limited as an example ... discusses options considered during the designprocess, the basis for the decisions made, and implementation details . . . describescontemporary RISC architecture, comparing and contrasting different designs ... andlooks at future trends in RISC research.Discussing the topic cohesively and comprehensively-from initial study into reducedinstructions sets to the widespread introduction of RISC architectures into mainstreamcomputer products-VLSI RISC Architecture and Organization is aninvaluable reference for electrical, electronics, and computer engineers; computerarchitects and scientists; hardware systems designers; and upper-level undergraduate andgraduate students in computer science and electrical engineering courses
Author: Kenzo Watanabe
Publisher: Nova Science Publishers
ISBN: 9781606920756
Category : Computer architecture
Languages : en
Pages : 0
Get Book Here
Book Description
Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. This book covers the ontology of computer-aided design, MOSFET's programmable conductance, vision-based path planning with onboard VLSI array processors, and much more.
Author: H.T. Kung
Publisher: Springer Science & Business Media
ISBN: 3642684025
Category : Technology & Engineering
Languages : en
Pages : 426
Get Book Here
Book Description
The papers in this book were presented at the CMU Conference on VLSI Systems and Computations, held October 19-21, 1981 in Pittsburgh, Pennsylvania. The conference was organized by the Computer Science Department, Carnegie-Mellon University and was partially supported by the National Science Foundation and the Office of Naval Research. These proceedings focus on the theory and design of computational systems using VLSI. Until very recently, integrated-circuit research and development were concentrated in the device physics and fabrication design disciplines and in the integrated-circuit industry itself. Within the last few years, a community of researchers is growing to address issues closer to computer science: the relationship between computing structures and the physical structures that implement them; the specification and verification of computational procosses implemented in VLSI; the use of massively parallel computing made possible by VLSI; the design of special purpose computing architectures; and the changes in general-purpose computer architecture that VLSI makes possible. It is likely that the future exploitation of VLSI technology depends as much on structural and design innovations as on advances in fabrication technology. The book is divided into nine sections: - Invited Papers. Six distinguished researchers from industry and academia presented invited papers. - Models of Computation. The papers in this section deal with abstracting the properties of VLSI circuits into models that can be used to analyze the chip area, time or energy required for a particular computation.
Author: Brian Randell
Publisher: Prentice Hall International (UK)
ISBN:
Category : Computers
Languages : en
Pages : 456
Get Book Here
Book Description
Author: Francisco Javier Ortiz Cerecedo
Publisher:
ISBN:
Category : Integrated circuits
Languages : es
Pages :
Get Book Here
Book Description
