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Author: Zuow-Zun Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 100
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Book Description
Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented. Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to TDCs in the past that concentrate on the arrival time difference between the divider feedback edge and the reference signal edge. Our approach extracts the timing information that is embedded in voltage domain. This approach not only achieves a higher time resolution, lower phase noise, but also consumes less power. A digital background calibration circuit is also presented to reduce the output spurious tones when the digital PLL operates under fractional-N divisions. Ring Oscillators (ROs) have the advantage of small area, wide tuning range, and multiphase output. However, their higher phase noise and higher sensitivity to supply noise may seriously deteriorate the wanted signal in wireless receivers. To circumvent this non-ideality, a low overhead phase noise cancellation technique for ring oscillator-based quadrature receivers is presented. The proposed technique operates in background and extracts ring oscillator phase noise as well as supply-induced phase noise from the digital PLL. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. In recent years, the unsilenced band at 57~64 GHz frequency range has motivated the building of high-data rate radio systems targeting wireless personal area network (WPAN) applications. To address this demand, a low-noise wide-band integer-N PLL is presented which serves as the carrier generator of a 60 GHz heterogeneous transceiver. The PLL employs sub-sampling phase detection technique to achieve low-noise performance, and provides 48 GHz LO and 12 GHz IF carrier signals for the heterogeneous transceiver.
Author: Zuow-Zun Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 100
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Book Description
Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented. Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to TDCs in the past that concentrate on the arrival time difference between the divider feedback edge and the reference signal edge. Our approach extracts the timing information that is embedded in voltage domain. This approach not only achieves a higher time resolution, lower phase noise, but also consumes less power. A digital background calibration circuit is also presented to reduce the output spurious tones when the digital PLL operates under fractional-N divisions. Ring Oscillators (ROs) have the advantage of small area, wide tuning range, and multiphase output. However, their higher phase noise and higher sensitivity to supply noise may seriously deteriorate the wanted signal in wireless receivers. To circumvent this non-ideality, a low overhead phase noise cancellation technique for ring oscillator-based quadrature receivers is presented. The proposed technique operates in background and extracts ring oscillator phase noise as well as supply-induced phase noise from the digital PLL. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. In recent years, the unsilenced band at 57~64 GHz frequency range has motivated the building of high-data rate radio systems targeting wireless personal area network (WPAN) applications. To address this demand, a low-noise wide-band integer-N PLL is presented which serves as the carrier generator of a 60 GHz heterogeneous transceiver. The PLL employs sub-sampling phase detection technique to achieve low-noise performance, and provides 48 GHz LO and 12 GHz IF carrier signals for the heterogeneous transceiver.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
A frequency synthesizer is a control system which employs a reference signal from a component, such as a crystal oscillator, with excellent phase and frequency stability to synthesize higher frequencies with similarly desirable characteristics. Such a control system is at the heart of many communication schemes. Due to the digital circuitry used in frequency synthesis, it is relatively straightforward to synthesize frequencies at integer multiples of the reference signal frequency. A synthesizer which achieves this is called an integer-N frequency synthesizer. The main challenge in the design of integer-N synthesizers is to reduce phase noise introduced by circuitry while achieving a needed frequency resolution. Noise can be spectrally spread by conversions in the loop which are non-linear, so the strategy to reduce noise is two-fold. Control-loop and circuit design techniques can be used to reduce device noise, but it is also important to make sure that the noise performance is not degraded by spectral spreading within the loop. This thesis addresses primarily the latter approach with the design and implementation of circuits targeting a specific conversion within the loop. Frequency resolution of a synthesizer can be improved by introducing additional circuitry and complexity. This additional complexity makes it possible to multiply the reference frequency by a fractional number and thus achieve higher frequency resolution. A control system which achieves this is called a fractional-N frequency synthesizer. The cost associated with the increased frequency resolution is a form of noise that is deterministic called spurious noise. This spurious noise can also be spread and amplified by non-linear conversions in the control loop. A quantitative understanding of the magnitude of this noise that is not readily available in the literature was developed in this research. A comparison between several implementations of integrated frequency synthesis was also carried out in this research with the intent of providing guidelines to produce a better performing synthesizer. These implementations differ in key components of the loop where linearity is of particular importance.
Author: Hamid R. Rategh
Publisher: Springer Science & Business Media
ISBN: 0792375335
Category : Computers
Languages : en
Pages : 157
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Book Description
Demand for wireless local area network systems has led to new frequency bands and new standards to accommodate higher data rates. Moreover, opportunities are increasing for the development of low- cost integrated WLAN systems. This guide for RF and high-speed analog circuit designers and students as well as wireless engineers studies the phase-locked loop as a basic building block of frequency synthesizers and WLAN receivers. It provides guidelines and engineering solutions for the design of loop filters in high- frequency PLLs. Rategh (Tavanza Inc.) and Lee (Stanford U.) discuss the different analog and digital frequency division techniques and introduce injection-locked frequency dividers as an alternative to conventional frequency dividers. c. Book News Inc.
Author: Ashok Swaminathan
Publisher:
ISBN:
Category :
Languages : en
Pages : 84
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Book Description
Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signals for use in wireless applications. To reduce the phase noise inherent to these systems, a digital-to-analog converter is used to cancel the error introduced by the fractional division process, however matching between the digital-to-analog converter and the phase-locked loop circuitry place a limit on the amount of phase noise reduction that can be achieved. Furthermore, circuit non-linearity results in the appearance of spurious tones in the phase-locked loop output. This dissertation outlines a calibration technique, and a digital quantization technique that provide solutions to these two problems. The calibration technique results in improved phase noise performance by adjusting the digital-to-analog converter gain, and thus providing better matching between the phase-locked loop circuitry and digital-to-analog converter. The digital quantization technique results in no spurious tones when specified non-linearity is applied to the quantizer output sequence and error. The calibration technique was implemented in an integrated circuit, which achieves state-of-the-art performance when compared to currently published phase-locked loops and allows for all circuitry to be integrated onto a single chip. Chapter 1 presents the calibration technique, as well as a theoretical analysis of the stability. Chapter 2 presents details on the digital quantization technique, and a mathematical proof of the absence of spurious tones. In chapter 3, results from an implemented circuit are presented, which verify the behaviour of the technique presented in chapter 1.
Author: 王俊彬
Publisher:
ISBN:
Category :
Languages : en
Pages :
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![An Adaptive Phase Quantization Noise Cancellation Architecture for [delta Sigma] Fractional-N Frequency Synthesizers PDF](https://books.google.com/books/content/images/frontcover/lZOvAQAACAAJ?fife=w80-h100)
Author: Jonathon Christopher Stiff
Publisher:
ISBN: 9781321738544
Category : Frequency synthesizers
Languages : en
Pages : 90
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Book Description
A fractional-N PLL phase quantization cancellation architecture using adaptive digital delay word scaling is presented and demonstrated. A digital sign-error adaptive filter utilizing the 1-bit quantized PLL phase error and the feedback divider delta-sigma modulator accumulated error generates the optimal control word scaling for a phase cancelling digital delay. A comprehensive analytic phase noise model is derived and compared to time-domain simulation and measurement. The proposed fractional-N synthesizer, with a 2.4 GHz center frequency VCO is fabricated on a PCB with commercially available integrated circuits as a proof of concept. The synthesizer output frequency range is 144-156 MHz with 2 ppm resolution for a 20 MHz crystal oscillator reference. The adaptive phase cancellation is measured to reduce phase noise by as much as 25 dB.
Author: Chih-Wei Yao
Publisher:
ISBN:
Category :
Languages : en
Pages : 101
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Book Description
This dissertation contains three parts. In the first part, the analysis and circuits of a jittercleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented. For the first part, the design utilizes a dual-loop architecture, which is suitable for integration in an SoC environment. The primary loop is a digital PLL with a second-order noise shaping phase-error ADC. The secondary loop is a fractional-N PLL implementing the digitally controlled oscillator inside the primary loop, and it locks to an external clean reference clock to reduce the phase noise and to improve the frequency stability of the on-chip oscillator. For the second part, a tail-tank coupling technique that combines two complementary differential LC-VCOs to form a quadrature LC-VCO is presented. This technique reduces phase noise by providing additional energy storages for noise redistribution and by canceling out most of the noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum value. For the third part, a 2.8 to 3.2 GHz fractional-N digital PLL is presented. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. An ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size to 20 kHz. With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, this prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. A FOM of -240.4 dB is achieved.
Author: Grigorios Kalivas
Publisher: John Wiley & Sons
ISBN: 9780470748374
Category : Technology & Engineering
Languages : en
Pages : 472
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Book Description
A systematic explanation of the principles of radio systems, Digital Radio System Design offers a balanced treatment of both digital transceiver modems and RF front-end subsystems and circuits. It provides an in-depth examination of the complete transceiver chain which helps to connect the two topics in a unified system concept. Although the book tackles such diverse fields it treats them in sufficient depth to give the designer a solid foundation and an implementation perspective. Covering the key concepts and factors that characterise and impact radio transmission and reception, the book presents topics such as receiver design, noise and distortion. Information is provided about more advanced aspects of system design such as implementation losses due to non-idealities. Providing vivid examples, illustrations and detailed case-studies, this book is an ideal introduction to digital radio systems design. Offers a balanced treatment of digital modem and RF front-end design concepts for complete transceivers Presents a diverse range of topics related to digital radio design including advanced transmission and synchronization techniques with emphasis on implementation Provides guidance on imperfections and non-idealities in radio system design Includes detailed design case-studies incorporating measurement and simulation results to illustrate the theory in practice
Author: Bar-Giora Goldberg
Publisher: Elsevier
ISBN: 0080504299
Category : Technology & Engineering
Languages : en
Pages : 354
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Book Description
· In-depth coverage of modern digital implementations of frequency synthesis architectures· Numerous design examples drawn from actual engineering projectsDigital frequency synthesis is used in modern wireless and communications technologies such as radar, cellular telephony, satellite communications, electronic imaging, and spectroscopy. This is book is a comprehensive overview of digital frequency synthesis theory and applications, with a particular emphasis on the latest approaches using fractional-N phase-locked loop technology. In-depth coverage of modern digital implementations of frequency synthesis architectures Numerous design examples drawn from actual engineering projects
![A Low Phase Noise Fast-settling PLL Frequency Synthesizer for CDMA Receivers [microform] PDF](https://books.google.com/books/content/images/frontcover/vyhknQAACAAJ?fife=w80-h100)
Author: Shaojun Wu
Publisher: Library and Archives Canada = Bibliothèque et Archives Canada
ISBN: 9780494019887
Category :
Languages : en
Pages : 182
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Book Description
