Author: Haiqiong Yao
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
Concurrent systems are getting more complex with the advent of multi-core processors and the support of concurrent programs. However, errors of concurrent systems are too subtle to detect with the traditional testing and simulation. Model checking is an effective method to verify concurrent systems by exhaustively searching the complete state space exhibited by a system. However, the main challenge for model checking is state explosion, that is the state space of a concurrent system grows exponentially in the number of components of the system. The state space explosion problem prevents model checking from being applied to systems in realistic size. After decades of intensive research, a large number of methods have been developed to attack this well-known problem. Compositional verification is one of the promising methods that can be scalable to large complex concurrent systems. In compositional verification, the task of verifying an entire system is divided into smaller tasks of verifying each component of the system individually. The correctness of the properties on the entire system can be derived from the results from the local verification on individual components. This method avoids building up the global state space for the entire system, and accordingly alleviates the state space explosion problem. In order to facilitate the application of compositional verification, several issues need to be addressed. The generation of over-approximate and yet accurate environments for components for local verification is a major focus of the automated compositional verification. This dissertation addresses such issue by proposing two abstraction refinement methods that refine the state space of each component with an over-approximate environment iteratively.
Author: Luciano Lavagno
Publisher: Springer Science & Business Media
ISBN: 1461532124
Category : Technology & Engineering
Languages : en
Pages : 353
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Book Description
Since the second half of the 1980s asynchronous circuits have been the subject of a great deal of research following a period of relative oblivion. The lack of interest in asynchronous techniques was motivated by the progressive shift towards synchronous design techniques that had much more structure and were much easier to verify and synthesize. System design requirements made it impossible to eliminate totally the use of asynchronous circuits. Given the objective difficulty encountered by designers, the asynchronous components of electronic systems such as interfaces became a serious bottleneck in the design process. The use of new models and some theoretical breakthroughs made it possible to develop asynchronous design techniques that were reliable and effective. This book describes a variety of mathematical models and of algorithms that form the backbone and the body of a new design methodology for asyn chronous design. The book is intended for asynchronous hardware designers, for computer-aided tool experts, and for digital designers interested in ex ploring the possibility of designing asynchronous circuits. It requires a solid mathematical background in discrete event systems and algorithms. While the book has not been written as a textbook, nevertheless it could be used as a reference book in an advanced course in logic synthesis or asynchronous design.
Author: Dominique Borrione
Publisher: Springer
ISBN: 354032030X
Category : Computers
Languages : en
Pages : 423
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Book Description
This book constitutes the refereed proceedings of the 13th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, CHARME 2005, held in Saarbrücken, Germany, in October 2005. The 21 revised full papers and 18 short papers presented together with 2 invited talks and one tutorial were carefully reviewed and selected from 79 submissions. The papers are organized in topical sections on functional approaches to design description, game solving approaches, abstraction, algorithms and techniques for speeding (DD-based) verification, real time and LTL model checking, evaluation of SAT-based tools, model reduction, and verification of memory hierarchy mechanisms.
Author: Sudipta Kundu
Publisher:
ISBN: 9781441993601
Category :
Languages : en
Pages : 184
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Book Description
Author: Tiziana Margaria
Publisher: Springer
ISBN: 3540447989
Category : Computers
Languages : en
Pages : 491
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Book Description
This volume contains the proceedings of CHARME 2001, the Eleventh Advanced Research Working Conference on Correct Hardware Design and Veri?cation Methods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the ‘CHARME’ series were held in Bad Herrenalb (1999), Montreal (1997), Frankfurt (1995), Arles (1993), and Torino (1991). This series of meetings has been organized in cooperation with IFIP WG 10.5 and WG 10.2. Prior meetings, stretching backto the earliest days of formal hardware veri?cation, were held under various names in Miami (1990), Leuven (1989), Glasgow (1988), Grenoble (1986), Edinburgh (1985), and Darmstadt (1984). The convention is now well-established whereby the European CHARME conference alternates with its biennial counterpart, the International Conference on Formal Methods in Computer-Aided Design (FMCAD), which is held on even-numbered years in the USA. The conference tookplace during 4–7 September 2001 at the Institute for System Level Integration in Livingston, Scotland. It was co-hosted by the - stitute and the Department of Computing Science of Glasgow University and co-sponsored by the IFIP TC10/WG10.5 Working Group on Design and En- neering of Electronic Systems. CHARME 2001 also included a scienti?c session and social program held jointly with the 14th International Conference on Th- rem Proving in Higher Order Logics (TPHOLs), which was co-located in nearby Edinburgh.
Author: Cuong Kim Chau
Publisher:
ISBN:
Category :
Languages : en
Pages : 288
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Book Description
The self-timed (or asynchronous) approach to circuit design has demonstrated benefits in a number of different areas for its low energy consumption, high operating speed, composability, and modularity. Nonetheless, the asynchronous paradigm exposes challenges that are not found in the synchronous (or clock-driven) paradigm. For the verification task, a challenge emerges from the large number of potential operational interleavings exhibited in the asynchronous paradigm. Simply exploring all interleavings is, in general, intractable because the number of interleavings can grow exponentially. This dissertation focuses on developing scalable methods that are capable of reasoning effectively about the interleaving problem exhibited in self-timed systems. We specify and verify finite-state-machine representations of self-timed circuit designs using the DE system, a formal hardware description language defined using the ACL2 theorem-proving system. We apply a link-joint paradigm to model self-timed circuits as networks of channels that communicate with each other locally via handshake protocols. This link-joint model has been shown to be a universal model for various self-timed circuit families. In addition, this model has a clean formalization in the ACL2 logic and provides a protocol level that abstracts away timing constraints at the circuit level. Unlike many efforts for validating timing and communication properties of self-timed systems, we are interested in verifying functional properties. Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences. To mitigate the consideration of all interleavings simultaneously, we address the verification problem hierarchically and avoid exploring the internal structures of verified submodules as well as their operational interleavings. The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting away all execution paths internal to that submodule
Author: Daniel Geist
Publisher: Springer Science & Business Media
ISBN: 354020363X
Category : Computers
Languages : en
Pages : 439
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Book Description
This book constitutes the refereed proceedings of the 12th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, CHARME 2003, held in L'Aquila, Italy in October 2003. The 24 revised full papers and 8 short papers presented were carefully reviewed and selected from 65 submissions. The papers are organized in topical sections on software verification, automata based methods, processor verification, specification methods, theorem proving, bounded model checking, and model checking and applications.
Author: Vikas S. Vij
Publisher:
ISBN:
Category : Asynchronous circuits
Languages : en
Pages : 207
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Book Description
Author: Alessandro Cimatti
Publisher: Springer
ISBN: 3319661973
Category : Computers
Languages : en
Pages : 427
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Book Description
This book constitutes the refereed proceedings of the 15th International Conference on Software Engineering and Formal Methods, SEFM 2017, held in Trento, Italy, in September 2017. The 17 full papers and 6 short papers presented were carefully reviewed and selected from 102 submissions. The papers deal with a large range of topics in the following research areas: new frontiers in software architecture; software verification and testing; software development methods; application and technology transfer; security and safety; and design principles.
Author: Jens Sparsø
Publisher: Springer Science & Business Media
ISBN: 1475733852
Category : Technology & Engineering
Languages : en
Pages : 348
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Book Description
Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors. The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.
