Hot-carrier Reliability Assessment in CMOS Digital Integrated Circuits PDF Download
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Author: Wenjie Jiang
Publisher:
ISBN:
Category :
Languages : en
Pages : 218
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Book Description
Author: Wenjie Jiang
Publisher:
ISBN:
Category :
Languages : en
Pages : 218
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Book Description
Author: Jone Fang Chen
Publisher:
ISBN:
Category :
Languages : en
Pages : 242
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Book Description
Author: Vei-Han Chan
Publisher:
ISBN:
Category :
Languages : en
Pages : 148
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Book Description
Author: Yusuf Leblebici
Publisher: Springer Science & Business Media
ISBN: 1461532507
Category : Technology & Engineering
Languages : en
Pages : 223
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Book Description
As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. Hot-carrier induced degrada tion of MOS transistor characteristics is one of the primary mechanisms affecting the long-term reliability of MOS VLSI circuits. It is likely to become even more important in future generation chips, since the down ward scaling of transistor dimensions without proportional scaling of the operating voltage aggravates this problem. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.
Author: Khandker Nazrul Quader
Publisher:
ISBN:
Category :
Languages : en
Pages : 368
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Book Description
Author: Elie Maricau
Publisher: Springer Science & Business Media
ISBN: 1461461634
Category : Technology & Engineering
Languages : en
Pages : 208
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Book Description
This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.
Author: Miloš Stanisavljević
Publisher: Springer Science & Business Media
ISBN: 1441962174
Category : Technology & Engineering
Languages : en
Pages : 215
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Book Description
This book is intended to give a general overview of reliability, faults, fault models, nanotechnology, nanodevices, fault-tolerant architectures and reliability evaluation techniques. Additionally, the book provides an in depth state-of-the-art research results and methods for fault tolerance as well as the methodology for designing fault-tolerant systems out of highly unreliable components.
Author: Bruce W. McGaughy
Publisher:
ISBN:
Category :
Languages : en
Pages : 70
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Book Description
Author: Sung-Mo Kang
Publisher: McGraw-Hill Science, Engineering & Mathematics
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 698
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Book Description
The second edition of this comprehensive text contains extensive revisions to reflect recent advances in technology and in circuit design practices. Recognizing that the area of digital integrated circuit design is evolving at an increasingly fast pace, every effort has been made to present state-of-the-art material on all subjects covered in the book. This book is primarily designed as a comprehensive text for senior level and first-year graduate level digital circuit design classes, as well as a reference for practicing engineers in the areas of IC design and VLSI.
Author: Weishi Sun
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
The goals of the research work presented in this thesis are to model submicron pMOS transistor hot-carrier degradation and to develop a fast reliability simulation tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently. As device sizes shrink into the submicron region, pMOS transistor hot-carrier degradation becomes increasingly more important. There has not, however, been a widely accepted model for pMOS transistor hot-carrier degradation unlike that for nMOS transistors. Existing reliability simulations tools are primarily based on transistor level simulation and, therefore, can not handle large circuits efficiently. Using the fast-timing-based reliability simulator, ILLIADS-R, and the empirical model developed based on our experimental results, hot-carrier reliability can be well predicted. ILLIADS-R also serves as an integral part of the hierarchical design-for-reliability system. A new hot-carrier degradation model is developed for submicron pMOS transistors. Using this model, the pMOS transistor hot-carrier degradation can be predicted based on the total injected charge into the gate oxide region and the initial gate current under normal operating condition. This model is integrated into the fast-timing-based reliability simulation tool, ILLIADS-R. The simulation results demonstrate that ILLIADS-R outperforms the existing reliability simulator BERT in terms of simulation speed with a comparable accuracy. Also studied are the pMOS transistor subthreshold leakage characteristics as a function of hot-carrier stress conditions. It is shown that subthreshold leakage current is a future limit to the pMOS device lifetime.
