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Author:
Publisher:
ISBN:
Category : Carbon nanotubes
Languages : en
Pages : 124
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Book Description
We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the carbon nanotube field-effect transistor (CNFET) technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. Our developed models are correlated with SPICE simulations using different types of gates and circuits with an average error of 3% and 5% for ideal and realistic cases respectively. Our framework is capable of estimating performance more than 100x faster as compared to SPICE simulations methods. Furthermore, using our models (PALE and PAPF), we present an optimization tool to minimize the area and delay product (ADP) of CNFET circuits. We deploy circuit-level techniques (CLT) prior to optimizing the tubes (CNTs) in the logic gates to achieve highly optimized solution with global approach. Finally, we propose more accurate probabilistic model for yield estimation which incorporates the impact of screening effect on the functional yield after the removal of metallic tubes.
Author:
Publisher:
ISBN:
Category : Carbon nanotubes
Languages : en
Pages : 124
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Book Description
We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the carbon nanotube field-effect transistor (CNFET) technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. Our developed models are correlated with SPICE simulations using different types of gates and circuits with an average error of 3% and 5% for ideal and realistic cases respectively. Our framework is capable of estimating performance more than 100x faster as compared to SPICE simulations methods. Furthermore, using our models (PALE and PAPF), we present an optimization tool to minimize the area and delay product (ADP) of CNFET circuits. We deploy circuit-level techniques (CLT) prior to optimizing the tubes (CNTs) in the logic gates to achieve highly optimized solution with global approach. Finally, we propose more accurate probabilistic model for yield estimation which incorporates the impact of screening effect on the functional yield after the removal of metallic tubes.
Author: Albert Lin
Publisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 166
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Book Description
Carbon Nanotube Field Effect Transistor (CNFET) technology has received a lot of attention in the past few years as a promising extension to silicon-CMOS for future digital logic integrated circuits. While recent research has advanced CNFET technology past many important milestones, robust and scalable solutions must be developed to realize the full potential of CNFETs. Thus, this thesis aims to develop a suite of techniques, spanning from material synthesis to circuit solutions, compatible with very-large-scale integration (VLSI). Specifically, to enable the real-world engineering of carbon nanotube integrated circuits, this thesis presents (1) wafer-scale aligned CNT growth, (2) wafer-scale CNT Transfer, (3) wafer-scale device and circuit fabrication techniques, and (4) ACCNT, a VLSI-compatible circuit design solution to surmounting the problem of metallic CNTs. These techniques culminated in the successful demonstration of CNT transistors, inverters, and NAND logic gates on a wafer scale. Furthermore, this thesis sheds light on important design considerations for the demonstration of a simple CNT "computer" and suggests a few critical directions for future work in the field of carbon nanotube technology. In contributing the above, this thesis hopes to propel carbon nanotube technology forward towards the vision of robust, large-scale integrated circuits using high-density carbon nanotubes.
Author: K. Sridharan
Publisher: Springer Nature
ISBN: 3030506991
Category : Technology & Engineering
Languages : en
Pages : 122
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Book Description
This book introduces readers to the emerging carbon nanotube field-effect transistor (CNTFET) technology, and examines the problem of designing efficient arithmetic circuits in CNTFET technology. Observing that CNTFETs make it possible to achieve two distinct threshold voltages merely by altering the diameter of the carbon nanotube used, the book begins by discussing the design of basic ternary logic elements. It then examines efficient CNTFET-based design of single and multiple ternary digit adders by judicious choice of unary operators in ternary logic, as well as the design of a ternary multiplier in CNTFET technology, and presents detailed simulation results in HSPICE. Lastly, the book outlines a procedure for automating the synthesis process and provides sample code in Python.
Author: Rehman Ashraf
Publisher:
ISBN:
Category : Carbon
Languages : en
Pages : 176
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Book Description
Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed. An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates.
Author: Jie Zhang
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
Carbon Nanotube Field Effect Transistors (CNFETs) are excellent candidates for building highly energy-efficient future electronic systems. Variations specific to carbon nanotubes (CNTs) pose major obstacles to energy-efficient and robust CNFET digital VLSI. CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. CNT processing techniques alone are inadequate to overcome these challenges. We present an integrated approach, combining CNFET modeling, processing and circuit design, to create VLSI circuits tolerant to CNT variations. Probabilistic models, calibrated using experimental data, are used to analyze the effects of two major sources of CNT variations: metallic CNTs (CNTs with no / very small bandgaps) and grown CNT density variations (due to the non-uniformity in CNT positioning). Using these models, we create a probabilistic framework to derive simple yet useful CNFET processing and circuit design guidelines to overcome CNT variations. The effectiveness of this approach is demonstrated using two examples: 1. CNT variations result in functional failures of CNFET circuits. The failure probability may be reduced through CNFET sizing but at substantial energy costs. A new layout design technique, which engineers correlation among various CNFETs, reduces CNFET circuit failure probability at significantly lower costs. 2. For the first time, the impact of CNT variations on delay variations of CNFET circuits is quantified. We explore the space of CNFET sizing, together with various possibilities to improve CNFET processing, to minimize circuit delay variations at low energy costs.
Author: Ashok Srivastava
Publisher: CRC Press
ISBN: 9814613118
Category : Science
Languages : en
Pages : 153
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Book Description
Discovery of one-dimensional material carbon nanotubes in 1991 by the Japanese physicist Dr. Sumio Iijima has resulted in voluminous research in the field of carbon nanotubes for numerous applications, including possible replacement of silicon used in the fabrication of CMOS chips. One interesting feature of carbon nanotubes is that these can be me
Author: Ali Javey
Publisher: Springer Science & Business Media
ISBN: 0387692851
Category : Technology & Engineering
Languages : en
Pages : 275
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Book Description
This book provides a complete overview of the field of carbon nanotube electronics. It covers materials and physical properties, synthesis and fabrication processes, devices and circuits, modeling, and finally novel applications of nanotube-based electronics. The book introduces fundamental device physics and circuit concepts of 1-D electronics. At the same time it provides specific examples of the state-of-the-art nanotube devices.
Author:
Publisher:
ISBN:
Category : Carbon nanotubes
Languages : en
Pages : 0
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Book Description
Various emerging technologies have shown great potential of supplementing silicon transistors as Moore's law slows down. One such disruptive technology, Carbon Nanotube Field Effect Transistors (CNFET), among others, promises increased speed and integration with reduced power consumption. However, due to a limited controllability over the Carbon Nano-tube(CNT) growth process, CNFETs show large variations in their performance and behavior. It is therefore difficult to predict and model their behavior while design suggestions are also challenging. CNT variations are important for a realistic delay modelling. Due to the presence of CNT-specific variations, conventional CMOS evaluation techniques cannot be used for CNFETs. Redundancy, however, comes at the cost of increased power and area. To limit redundancy, we propose adding redundant tubes only to transistors on critical paths. The challenge with this approach is that with variations, critical paths may vary under CNT variations. Therefore, to consider all potential critical paths under assumed variations and add redundancy to all of them, we developed an efficient algorithm for fast identification of all paths that can become critical in the presence of variations.
Author: Raj, Balwinder
Publisher: IGI Global
ISBN: 1799813959
Category : Technology & Engineering
Languages : en
Pages : 255
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Book Description
With recent advancements in electronics, specifically nanoscale devices, new technologies are being implemented to improve the properties of automated systems. However, conventional materials are failing due to limited mobility, high leakage currents, and power dissipation. To mitigate these challenges, alternative resources are required to advance electronics further into the nanoscale domain. Carbon nanotube field-effect transistors are a potential solution yet lack the information and research to be properly utilized. Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET) is a collection of innovative research on the methods and applications of converting semiconductor devices from micron technology to nanotechnology. The book provides readers with an updated status on existing CNTs, CNTFETs, and their applications and examines practical applications to minimize short channel effects and power dissipation in nanoscale devices and circuits. While highlighting topics including interconnects, digital circuits, and single-wall CNTs, this book is ideally designed for electrical engineers, electronics engineers, students, researchers, academicians, industry professionals, and practitioners working in nanoscience, nanotechnology, applied physics, and electrical and electronics engineering.
Author: Yu Cao
Publisher: Springer Science & Business Media
ISBN: 1461404452
Category : Technology & Engineering
Languages : en
Pages : 186
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Book Description
Predictive Technology Model for Robust Nanoelectronic Design explains many of the technical mysteries behind the Predictive Technology Model (PTM) that has been adopted worldwide in explorative design research. Through physical derivation and technology extrapolation, PTM is the de-factor device model used in electronic design. This work explains the systematic model development and provides a guide to robust design practice in the presence of variability and reliability issues. Having interacted with multiple leading semiconductor companies and university research teams, the author brings a state-of-the-art perspective on technology scaling to this work and shares insights gained in the practices of device modeling.
