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Author: Benwei Xu
Publisher:
ISBN:
Category : Multiplexing
Languages : en
Pages :
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Book Description
The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over 20GS/s is one key enabler. For 5G wireless communication system high resolution ADC (12bit) with sampling speed over 1GHz is required. Many other application also demands ADC with performance that has never been achieved before while only provides a strict power budget. Time-interleaving massive slow-but-efficient subADCs to achieve the target is one practical way. However, the benefit brought by time-interleaving is not free. Mismatch between subADCs often limits its linearity making the performance of the array far from the individual subADCs. Among all different kinds of mismatches, dynamic mismatch including skew and bandwidth mismatch are the hardest to identify and cure. This dissertation will introduce two different methods to calibrate the skew mismatch of TI-ADC. Two fabricated chip 12b 1GS/s and 6b 24GS/s will be shown as the silicon verification of the proposed methods.
Author: Benwei Xu
Publisher:
ISBN:
Category : Multiplexing
Languages : en
Pages :
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Book Description
The emerging applications such as Internet-of-Things (IoT), self-driven car and artificial intelligence (AI) trigger rapid increase in bandwidth demand in data centers and telecommunication infrastructure. The data traffic in global network is expected to be tripled by 2020 and the ITRS predicts the IO speed to exceed 60GB/s in 2020. ADC-based backplane receivers and coherent fiber-optical receivers are promising technologies for the next generation wireline communication systems. For both technologies, high speed analog-to-digital converter (ADC) of over 20GS/s is one key enabler. For 5G wireless communication system high resolution ADC (12bit) with sampling speed over 1GHz is required. Many other application also demands ADC with performance that has never been achieved before while only provides a strict power budget. Time-interleaving massive slow-but-efficient subADCs to achieve the target is one practical way. However, the benefit brought by time-interleaving is not free. Mismatch between subADCs often limits its linearity making the performance of the array far from the individual subADCs. Among all different kinds of mismatches, dynamic mismatch including skew and bandwidth mismatch are the hardest to identify and cure. This dissertation will introduce two different methods to calibrate the skew mismatch of TI-ADC. Two fabricated chip 12b 1GS/s and 6b 24GS/s will be shown as the silicon verification of the proposed methods.
Author: Ming Qiang Guo
Publisher:
ISBN:
Category :
Languages : en
Pages : 104
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Book Description
Author: Christopher Kaiti Su
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
Author: Dusan Vlastimir Stepanovic
Publisher:
ISBN:
Category :
Languages : en
Pages : 228
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Book Description
Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
Author: Weitao Li
Publisher: Springer
ISBN: 3319620126
Category : Technology & Engineering
Languages : en
Pages : 181
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Book Description
This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Author: Christopher Leonidas David
Publisher:
ISBN:
Category :
Languages : en
Pages : 370
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Book Description
Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Author: Yun-Shiang Shu
Publisher:
ISBN:
Category :
Languages : en
Pages : 111
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Book Description
A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband communication transceivers, video imaging systems, and instrumentation. As the ADC speed increases with the advances in IC fabrication technology, the ADC resolution is still limited by the non-ideal effects of the circuits, such as device inaccuracy, component mismatch, and finite device gain. A recent trend for enhancing the resolution is to calibrate the non-ideal effects in background with the aid of digital signal processing. These techniques are preferred since the calibration accuracy is not limited by the accuracy of the analog components, and the calibration tracks the variations of process, voltage and temperature without interrupting ADC's normal operation. This dissertation describes the background calibration techniques for three high-speed, high-resolution ADCs using different architectures: pipelined, floating-point, and continuous-time (CT) [delta]-[sigma]. For pipelined ADCs, a background digital calibration technique with signal-dependent dithering scheme is proposed to overcome the dither magnitude and measurement time constraints with the existing fixed-magnitude dithering. A 15-b, 20-MS/s prototype ADC achieves a spurious-free dynamic range (SFDR) of 98 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 73 dB. The chip is fabricated in 0.18-um complementary metal-oxide-semiconductor (CMOS) process, occupies an active area of 2.3 x 1.7 mm2, and consumes 285 mW at 1.8 V. The concept of signal-dependent dithering is also applied to a floating-point ADC (FADC) to calibrate the gain and offset errors in the variable gain amplifier (VGA) stages. A digitally-calibrated 10~15-b 60-MS/s FADC adjusts its quantization steps instantly depending on the sampled input level and enhances the integral non-linearity (INL) from 24 to 0.9 least significant bit (LSB) at a 15-b level for small input signals. The chip is fabricated in 0.18-um CMOS process, occupies 3.5 x 2.5 mm2, and consumes 300 mW at 1.8 V. In the CT [delta]-[sigma] architecture, the active filter is calibrated by injecting a binary pulse dither and nulling it with an LMS algorithm. The proposed technique calibrates the filter time-constant continuously with crystal accuracy, while the conventional master-slave approaches use additional analog components which limit the calibration accuracy. A 3rd-order 4-b prototype in 65-nm CMOS occupies 0.5 mm2 and consumes 50 mW at 1.3 V. It achieves a dynamic range (DR) of 81 dB over an 8-MHz signal bandwidth with a 2.4 Vpp full-scale range. Signal-to-noise ratio (SNR) and SNDR at -1 dBFS are 76 and 70 dB, respectively.
Author: Xiao Wang
Publisher:
ISBN:
Category :
Languages : en
Pages : 93
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Book Description
Time-Interleaving (TI) can relax the power-speed tradeoffs of analog-to-digital converter (ADC) and reduce their metastability error rate while it is not free. Track-and-hold (T&H) nonlinearity, noise and power are the main limitations of high-speed high-resolution and low-power ADCs. This dissertation introduces two efficient T&H design techniques to improve the performances of TI-ADCs without sophisticated calibrations. Two fabricated chips with 8b 2GS/s and 8b 8.8GS/s will be shown as the silicon verification of the proposed methods. Two prototype ICs were designed during this work. First, a two-way time-interleaved pipelined ADC architecture was built upon a new concept of virtual-ground sampling, featuring merged front-end T/H, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the THD, bandwidth, and sample rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in a 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency. Second, a complementary dual-loop-assisted track-and-hold buffer is introduced to achieve both high linearity and bandwidth with low power. The prototype ADC also employs a two-level 2i 8 master-slave hierarchical interleaved architecture and achieved an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. It achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
Author: Daniel Prashanth Kumar
Publisher:
ISBN:
Category :
Languages : en
Pages : 160
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Book Description
There is an ever-increasing demand for high-resolution and high-resolution ADCs. In order to raise the sampling rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given technology, mismatch issues such as gain, offset, and sampling clock skew between channels degrade the overall time-interleaved ADC performance. Of these issues, sampling clock skew between channels is the biggest problem in high-speed and high-resolution, time-interleaved ADCs as errors due to sampling clock skew become more severe for higher input frequencies. There are a few sources of sampling clock skew between channels. Mismatches in the sampling clock path and logic delays are the most obvious ones. Input signal routing mismatch and RC mismatch of the input sampling circuits also cause sampling clock skew. In this thesis, we developed two new methods to mitigate the effects of sampling clock skew in time-interleaved ADCs. The first is the rapid consecutive sampling method, whereby each interleaved channel is implemented using two sub-channel ADCs. Two consecutive samples of the input are taken with a short time delay between them. This allows for a straight-forward linear interpolation between the consecutive samples in order to recover the de-skewed sample. The second method entails introducing a programmable delay in the input signal path, instead of delaying the sampling clock, in order to calibrate out sampling clock skew. The design and implementation of a proof-of-concept, time-interleaved ADC that implements the input signal delay method is detailed. Finally, measurement results to show the efficacy of the proposed method in mitigating the effects of sampling clock skew is also presented.
Author: Sai-Weng Sin
Publisher: Springer Science & Business Media
ISBN: 9048197104
Category : Technology & Engineering
Languages : en
Pages : 147
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Book Description
Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
