Author: Malek Safieh
Publisher: Springer Nature
ISBN: 3658344598
Category : Computers
Languages : en
Pages : 155
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Book Description
In this work, algorithms and architectures for cryptography and source coding are developed, which are suitable for many resource-constrained embedded systems such as non-volatile flash memories. A new concept for elliptic curve cryptography is presented, which uses an arithmetic over Gaussian integers. Gaussian integers are a subset of the complex numbers with integers as real and imaginary parts. Ordinary modular arithmetic over Gaussian integers is computational expensive. To reduce the complexity, a new arithmetic based on the Montgomery reduction is presented. For the elliptic curve point multiplication, this arithmetic over Gaussian integers improves the computational efficiency, the resistance against side channel attacks, and reduces the memory requirements. Furthermore, an efficient variant of the Lempel-Ziv-Welch (LZW) algorithm for universal lossless data compression is investigated. Instead of one LZW dictionary, this algorithm applies several dictionaries to speed up the encoding process. Two dictionary partitioning techniques are introduced that improve the compression rate and reduce the memory size of this parallel dictionary LZW algorithm.
Author: Malek Safieh
Publisher:
ISBN: 9783658344603
Category :
Languages : en
Pages : 0
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Book Description
In this work, algorithms and architectures for cryptography and source coding are developed, which are suitable for many resource-constrained embedded systems such as non-volatile flash memories. A new concept for elliptic curve cryptography is presented, which uses an arithmetic over Gaussian integers. Gaussian integers are a subset of the complex numbers with integers as real and imaginary parts. Ordinary modular arithmetic over Gaussian integers is computational expensive. To reduce the complexity, a new arithmetic based on the Montgomery reduction is presented. For the elliptic curve point multiplication, this arithmetic over Gaussian integers improves the computational efficiency, the resistance against side channel attacks, and reduces the memory requirements. Furthermore, an efficient variant of the Lempel-Ziv-Welch (LZW) algorithm for universal lossless data compression is investigated. Instead of one LZW dictionary, this algorithm applies several dictionaries to speed up the encoding process. Two dictionary partitioning techniques are introduced that improve the compression rate and reduce the memory size of this parallel dictionary LZW algorithm. About the Author Malek Safieh is a research scientist in the field of cryptography and data compression.
Author: Charles Ching-hsiang Hsu
Publisher: World Scientific
ISBN: 9814460923
Category : Technology & Engineering
Languages : en
Pages : 319
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Book Description
Would you like to add the capabilities of the Non-Volatile Memory (NVM) as a storage element in your silicon integrated logic circuits, and as a trimming sector in your high voltage driver and other silicon integrated analog circuits? Would you like to learn how to embed the NVM into your silicon integrated circuit products to improve their performance?This book is written to help you.It provides comprehensive instructions on fabricating the NVM using the same processes you are using to fabricate your logic integrated circuits. We at our eMemory company call this technology the embedded Logic NVM. Because embedded Logic NVM has simple fabrication processes, it has replaced the conventional NVM in many traditional and new applications, including LCD driver, LED driver, MEMS controller, touch panel controller, power management unit, ambient and motion sensor controller, micro controller unit (MCU), security ID setting tag, RFID, NFC, PC camera controller, keyboard controller, and mouse controller. The recent explosive growth of the Logic NVM indicates that it will soon dominate all NVM applications. The embedded Logic NVM was invented and has been implemented in users' applications by the 200+ employees of our eMemory company, who are also the authors and author-assistants of this book.This book covers the following Logic NVM products: One Time Programmable (OTP) memory, Multiple Times Programmable (MTP) memory, Flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM). The fundamentals of the NVM are described in this book, which include: the physics and operations of the memory transistors, the basic building block of the memory cells and the access circuits.All of these products have been used continuously by the industry worldwide. In-depth readers can attain expert proficiency in the implementation of the embedded Logic NVM technology in their products.
Author: Seungbum Hong
Publisher: Springer
ISBN: 1489975373
Category : Technology & Engineering
Languages : en
Pages : 280
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Book Description
This book is an introduction to the fundamentals of emerging non-volatile memories and provides an overview of future trends in the field. Readers will find coverage of seven important memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), Multiferroic RAM (MFRAM), Phase-Change Memories (PCM), Oxide-based Resistive RAM (RRAM), Probe Storage, and Polymer Memories. Chapters are structured to reflect diffusions and clashes between different topics. Emerging Non-Volatile Memories is an ideal book for graduate students, faculty, and professionals working in the area of non-volatile memory. This book also: Covers key memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), and Multiferroic RAM (MFRAM), among others. Provides an overview of non-volatile memory fundamentals. Broadens readers’ understanding of future trends in non-volatile memories.
Author: Kohei Arai
Publisher: Springer Nature
ISBN: 3030801292
Category : Technology & Engineering
Languages : en
Pages : 1108
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Book Description
This book is a comprehensive collection of chapters focusing on the core areas of computing and their further applications in the real world. Each chapter is a paper presented at the Computing Conference 2021 held on 15-16 July 2021. Computing 2021 attracted a total of 638 submissions which underwent a double-blind peer review process. Of those 638 submissions, 235 submissions have been selected to be included in this book. The goal of this conference is to give a platform to researchers with fundamental contributions and to be a premier venue for academic and industry practitioners to share new ideas and development experiences. We hope that readers find this volume interesting and valuable as it provides the state-of-the-art intelligent methods and techniques for solving real-world problems. We also expect that the conference and its publications is a trigger for further related research and technology improvements in this important subject.
Author: Paulo Cappelletti
Publisher: Springer Science & Business Media
ISBN: 1461550157
Category : Technology & Engineering
Languages : en
Pages : 544
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Book Description
A Flash memory is a Non Volatile Memory (NVM) whose "unit cells" are fabricated in CMOS technology and programmed and erased electrically. In 1971, Frohman-Bentchkowsky developed a folating polysilicon gate tran sistor [1, 2], in which hot electrons were injected in the floating gate and removed by either Ultra-Violet (UV) internal photoemission or by Fowler Nordheim tunneling. This is the "unit cell" of EPROM (Electrically Pro grammable Read Only Memory), which, consisting of a single transistor, can be very densely integrated. EPROM memories are electrically programmed and erased by UV exposure for 20-30 mins. In the late 1970s, there have been many efforts to develop an electrically erasable EPROM, which resulted in EEPROMs (Electrically Erasable Programmable ROMs). EEPROMs use hot electron tunneling for program and Fowler-Nordheim tunneling for erase. The EEPROM cell consists of two transistors and a tunnel oxide, thus it is two or three times the size of an EPROM. Successively, the combination of hot carrier programming and tunnel erase was rediscovered to achieve a single transistor EEPROM, called Flash EEPROM. The first cell based on this concept has been presented in 1979 [3]; the first commercial product, a 256K memory chip, has been presented by Toshiba in 1984 [4]. The market did not take off until this technology was proven to be reliable and manufacturable [5].
Author: Jakub Szefer
Publisher: Springer Nature
ISBN: 3031017609
Category : Technology & Engineering
Languages : en
Pages : 154
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Book Description
With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.
Author: Brian Randell
Publisher: Prentice Hall International (UK)
ISBN:
Category : Computers
Languages : en
Pages : 456
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Book Description
Author: Rino Micheloni
Publisher: Springer
ISBN: 9401775125
Category : Computers
Languages : en
Pages : 391
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Book Description
This book walks the reader through the next step in the evolution of NAND flash memory technology, namely the development of 3D flash memories, in which multiple layers of memory cells are grown within the same piece of silicon. It describes their working principles, device architectures, fabrication techniques and practical implementations, and highlights why 3D flash is a brand new technology. After reviewing market trends for both NAND and solid state drives (SSDs), the book digs into the details of the flash memory cell itself, covering both floating gate and emerging charge trap technologies. There is a plethora of different materials and vertical integration schemes out there. New memory cells, new materials, new architectures (3D Stacked, BiCS and P-BiCS, 3D FG, 3D VG, 3D advanced architectures); basically, each NAND manufacturer has its own solution. Chapter 3 to chapter 7 offer a broad overview of how 3D can materialize. The 3D wave is impacting emerging memories as well and chapter 8 covers 3D RRAM (resistive RAM) crosspoint arrays. Visualizing 3D structures can be a challenge for the human brain: this is way all these chapters contain a lot of bird’s-eye views and cross sections along the 3 axes. The second part of the book is devoted to other important aspects, such as advanced packaging technology (i.e. TSV in chapter 9) and error correction codes, which have been leveraged to improve flash reliability for decades. Chapter 10 describes the evolution from legacy BCH to the most recent LDPC codes, while chapter 11 deals with some of the most recent advancements in the ECC field. Last but not least, chapter 12 looks at 3D flash memories from a system perspective. Is 14nm the last step for planar cells? Can 100 layers be integrated within the same piece of silicon? Is 4 bit/cell possible with 3D? Will 3D be reliable enough for enterprise and datacenter applications? These are some of the questions that this book helps answering by providing insights into 3D flash memory design, process technology and applications.
Author: Stallings
Publisher: Pearson Education India
ISBN: 9788177589931
Category :
Languages : en
Pages : 800
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Book Description
