Verilog Piecewise Linear Behavioral Modeling for Mixed-signal Validation PDF Download
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Author: Sabrina Liao
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Languages : en
Pages :
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Book Description
Mixed-signal systems-on-chip (SoC's) are complex entities that contain very tightly coupled analog and digital circuits. Validating these complex systems requires simulating the entire design through a large number of test vectors, and each test vector might in turn lead to a long simulation. Due to traditionally differing views of validation as well as design tools for analog and digital, validation of an SoC is not easy. Behavioral modeling is an attractive approach that tries to address this issue by replacing analog circuits with high-level functional models to speed up simulation while retaining some of the analog behavior. This dissertation proposes a method for creating these models in an event-driven, digital modeling language. Piecewise linear approximation is used to represent continuous time analog signals as value-slope pairs that update at discrete instances in time. By breaking analog circuits into sub-blocks with mostly unidirectional ports and leveraging the (nearly) linear intent of analog circuits, an efficient method of computing module output that avoids time integration is possible. The overall result is analog behavioral models that are pin-accurate, fast to simulate and capture the key dynamics in analog circuits. Models of various types of circuits (a simple RC filter, a phase interpolator, a comparator and a current DAC) are used to illustrate the wide applicability of the proposed modeling method. A 250MS/s track and hold, a 2.5-1.8V switching regulator, and a 1GHz PLL are also modeled to verify the preservation of important circuit behaviors as well as to gauge these models' computation complexity.
Author: Sabrina Liao
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
Mixed-signal systems-on-chip (SoC's) are complex entities that contain very tightly coupled analog and digital circuits. Validating these complex systems requires simulating the entire design through a large number of test vectors, and each test vector might in turn lead to a long simulation. Due to traditionally differing views of validation as well as design tools for analog and digital, validation of an SoC is not easy. Behavioral modeling is an attractive approach that tries to address this issue by replacing analog circuits with high-level functional models to speed up simulation while retaining some of the analog behavior. This dissertation proposes a method for creating these models in an event-driven, digital modeling language. Piecewise linear approximation is used to represent continuous time analog signals as value-slope pairs that update at discrete instances in time. By breaking analog circuits into sub-blocks with mostly unidirectional ports and leveraging the (nearly) linear intent of analog circuits, an efficient method of computing module output that avoids time integration is possible. The overall result is analog behavioral models that are pin-accurate, fast to simulate and capture the key dynamics in analog circuits. Models of various types of circuits (a simple RC filter, a phase interpolator, a comparator and a current DAC) are used to illustrate the wide applicability of the proposed modeling method. A 250MS/s track and hold, a 2.5-1.8V switching regulator, and a 1GHz PLL are also modeled to verify the preservation of important circuit behaviors as well as to gauge these models' computation complexity.
Author: Dan FitzPatrick
Publisher: Springer Science & Business Media
ISBN: 0306479184
Category : Technology & Engineering
Languages : en
Pages : 226
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Book Description
Analog Behavioral Modeling With The Verilog-A Language provides the IC designer with an introduction to the methodologies and uses of analog behavioral modeling with the Verilog-A language. In doing so, an overview of Verilog-A language constructs as well as applications using the language are presented. In addition, the book is accompanied by the Verilog-A Explorer IDE (Integrated Development Environment), a limited capability Verilog-A enhanced SPICE simulator for further learning and experimentation with the Verilog-A language. This book assumes a basic level of understanding of the usage of SPICE-based analog simulation and the Verilog HDL language, although any programming language background and a little determination should suffice. From the Foreword: `Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. Verilog-A provides a new dimension of design and simulation capability for analog electronic systems. Previously, analog simulation has been based upon the SPICE circuit simulator or some derivative of it. Digital simulation is primarily performed with a hardware description language such as Verilog, which is popular since it is easy to learn and use. Making Verilog more worthwhile is the fact that several tools exist in the industry that complement and extend Verilog's capabilities ... Behavioral Modeling With the Verilog-A Language provides a good introduction and starting place for students and practicing engineers with interest in understanding this new level of simulation technology. This book contains numerous examples that enhance the text material and provide a helpful learning tool for the reader. The text and the simulation program included can be used for individual study or in a classroom environment ...' Dr. Thomas A. DeMassa, Professor of Engineering, Arizona State University
Author: Sabrine Ben Yochret
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Author: Ken Kundert
Publisher: Springer Science & Business Media
ISBN: 140208045X
Category : Technology & Engineering
Languages : en
Pages : 281
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Book Description
The Verilog Hardware Description Language (Verilog-HDL) has long been the most popular language for describing complex digital hardware. It started life as a prop- etary language but was donated by Cadence Design Systems to the design community to serve as the basis of an open standard. That standard was formalized in 1995 by the IEEE in standard 1364-1995. About that same time a group named Analog Verilog International formed with the intent of proposing extensions to Verilog to support analog and mixed-signal simulation. The first fruits of the labor of that group became available in 1996 when the language definition of Verilog-A was released. Verilog-A was not intended to work directly with Verilog-HDL. Rather it was a language with Similar syntax and related semantics that was intended to model analog systems and be compatible with SPICE-class circuit simulation engines. The first implementation of Verilog-A soon followed: a version from Cadence that ran on their Spectre circuit simulator. As more implementations of Verilog-A became available, the group defining the a- log and mixed-signal extensions to Verilog continued their work, releasing the defi- tion of Verilog-AMS in 2000. Verilog-AMS combines both Verilog-HDL and Verilog-A, and adds additional mixed-signal constructs, providing a hardware description language suitable for analog, digital, and mixed-signal systems. Again, Cadence was first to release an implementation of this new language, in a product named AMS Designer that combines their Verilog and Spectre simulation engines.
Author: Ahmad Taher Azar
Publisher: Springer
ISBN: 3319502492
Category : Technology & Engineering
Languages : en
Pages : 873
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Book Description
The book reports on the latest advances in and applications of fractional order control and synchronization of chaotic systems, explaining the concepts involved in a clear, matter-of-fact style. It consists of 30 original contributions written by eminent scientists and active researchers in the field that address theories, methods and applications in a number of research areas related to fractional order control and synchronization of chaotic systems, such as: fractional chaotic systems, hyperchaotic systems, complex systems, fractional order discrete chaotic systems, chaos control, chaos synchronization, jerk circuits, fractional chaotic systems with hidden attractors, neural network, fuzzy logic controllers, behavioral modeling, robust and adaptive control, sliding mode control, different types of synchronization, circuit realization of chaotic systems, etc. In addition to providing readers extensive information on chaos fundamentals, fractional calculus, fractional differential equations, fractional control and stability, the book also discusses key applications of fractional order chaotic systems, as well as multidisciplinary solutions developed via control modeling. As such, it offers the perfect reference guide for graduate students, researchers and practitioners in the areas of fractional order control systems and fractional order chaotic systems.
Author: Sorin Alexander Huss
Publisher: Springer Science & Business Media
ISBN: 0306481014
Category : Technology & Engineering
Languages : en
Pages : 174
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Book Description
For the first time, this up-to-date text combines the main issues of the hardware description language VHDL-AMS aimed at model representation of mixed-signal circuits and systems, characterization methods and tools for the extraction of model parameters, and modelling methodologies for accurate high-level behavioural models.
Author: Janick Bergeron
Publisher: Springer Science & Business Media
ISBN: 0306476878
Category : Technology & Engineering
Languages : en
Pages : 373
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Book Description
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Protocol Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL Specific Filenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout
Author: Richard C.-J. Shi
Publisher:
ISBN:
Category :
Languages : en
Pages : 66
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Author: Institute of Electrical and Electronics Engineers
Publisher:
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Category :
Languages : en
Pages :
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Author: H. Alan Mantooth
Publisher:
ISBN:
Category :
Languages : en
Pages : 117
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Book Description
