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Author: Jozef Hooman
Publisher: Springer Science & Business Media
ISBN: 9783540549475
Category : Computers
Languages : en
Pages : 254
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Book Description
The research described in this monograph concerns the formal specification and compositional verification of real-time systems. A real-time programminglanguage is considered in which concurrent processes communicate by synchronous message passing along unidirectional channels. To specifiy functional and timing properties of programs, two formalisms are investigated: one using a real-time version of temporal logic, called Metric Temporal Logic, and another which is basedon extended Hoare triples. Metric Temporal Logic provides a concise notationto express timing properties and to axiomatize the programming language, whereas Hoare-style formulae are especially convenient for the verification of sequential constructs. For both approaches a compositional proof system has been formulated to verify that a program satisfies a specification. To deduce timing properties of programs, first maximal parallelism is assumed, modeling the situation in which each process has itsown processor. Next, this model is generalized to multiprogramming where several processes may share a processor and scheduling is based on priorities. The proof systems are shown to be sound and relatively complete with respect to a denotational semantics of the programming language. The theory is illustrated by an example of a watchdog timer.
Author: Jozef Hooman
Publisher: Springer Science & Business Media
ISBN: 9783540549475
Category : Computers
Languages : en
Pages : 254
Get Book Here
Book Description
The research described in this monograph concerns the formal specification and compositional verification of real-time systems. A real-time programminglanguage is considered in which concurrent processes communicate by synchronous message passing along unidirectional channels. To specifiy functional and timing properties of programs, two formalisms are investigated: one using a real-time version of temporal logic, called Metric Temporal Logic, and another which is basedon extended Hoare triples. Metric Temporal Logic provides a concise notationto express timing properties and to axiomatize the programming language, whereas Hoare-style formulae are especially convenient for the verification of sequential constructs. For both approaches a compositional proof system has been formulated to verify that a program satisfies a specification. To deduce timing properties of programs, first maximal parallelism is assumed, modeling the situation in which each process has itsown processor. Next, this model is generalized to multiprogramming where several processes may share a processor and scheduling is based on priorities. The proof systems are shown to be sound and relatively complete with respect to a denotational semantics of the programming language. The theory is illustrated by an example of a watchdog timer.
Author: Craig Silverman
Publisher:
ISBN: 9781312023130
Category : Attribution of news
Languages : en
Pages : 120
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Book Description
Author: Axel Legay
Publisher: Springer
ISBN: 3642407870
Category : Computers
Languages : en
Pages : 439
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Book Description
This book constitutes the refereed proceedings of the 4th International Conference on Runtime Verification, RV 2013, held in Rennes, France, in September 2013. The 24 revised full papers presented together with 3 invited papers, 2 tool papers, and 6 tutorials were carefully reviewed and selected from 58 submissions. The papers address a wide range of specification languages and formalisms for traces; specification mining; program instrumentation; monitor construction techniques; logging, recording, and replay; fault detection, localization, recovery, and repair; program steering and adaptation; as well as metrics and statistical information gathering; combination of static and dynamic analyses and program execution visualization.
Author: Martin Leucker
Publisher: Springer
ISBN: 3540892478
Category : Computers
Languages : en
Pages : 195
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Book Description
This book constitutes the thoroughly refereed post-proceedings of the 8th International Workshop on Runtime Verification, RV 2008, held in Budapest, Hungary, in March 2008 as satellite event of ETAPS 2008. The 9 revised full papers presented together with 2 invited papers were carefully selected from 27 initial submissions. The subject covers several technical fields such as runtime verification, runtime checking, runtime monitoring, and security and safety matters.
Author: Chris Spear
Publisher: Springer Science & Business Media
ISBN: 146140715X
Category : Technology & Engineering
Languages : en
Pages : 500
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Book Description
Based on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill. In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard Descriptions of UVM features such as factories, the test registry, and the configuration database Expanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
Author: Manfred Broy
Publisher: Springer Science & Business Media
ISBN: 3540262784
Category : Computers
Languages : en
Pages : 646
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Book Description
Testing is the primary hardware and software verification technique used by industry today. Usually, it is ad hoc, error prone, and very expensive. In recent years, however, many attempts have been made to develop more sophisticated formal testing methods. This coherent book provides an in-depth assessment of this emerging field, focusing on formal testing of reactive systems. This book is based on a seminar held in Dagstuhl Castle, Germany, in January 2004. It presents 19 carefully reviewed and revised lectures given at the seminar in a well-balanced way ensuring competent complementary coverage of all relevant aspects. An appendix provides a glossary for model-based testing and basics on finite state machines and on labelled transition systems. The lectures are presented in topical sections on testing of finite state machines, testing of labelled transition systems, model-based test case generation, tools and case studies, standardized test notation and execution architectures, and beyond testing.
Author: Borzoo Bonakdarpour
Publisher: Springer
ISBN: 3319111647
Category : Computers
Languages : en
Pages : 373
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Book Description
This book constitutes the refereed proceedings of the 5th International Conference on Runtime Verification, RV 2014, held in Toronto, ON, Canada in September 2014. The 28 revised full papers presented together with 2 tool papers, and 8short papers were carefully reviewed and selected from 70 submissions. The scope of the conference was on following topics: monitoring and trace slicing, runtime verification of distributed and concurrent systems, runtime Verification of real-time and embedded systems, testing and bug finding, and inference and learning.
Author: Howard Barringer
Publisher: Springer Science & Business Media
ISBN: 3642166113
Category : Computers
Languages : en
Pages : 503
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Book Description
This book constitutes the thoroughly refereed conference proceedings of the First International Conference on Runtime Verification, RV 2010, held in St. Julians, Malta, in November 2010. The 23 revised full papers presented together with 6 invited papers, 6 tutorials and 4 tool demonstrations were carefully reviewed and selected from 74 submissions. The papers address a wide range of topics such as runtime monitoring, analysis and verification, statically and dynamical, runtime simulations, together with applications in malware analysis and failure recovery, as well as execution tracing in embedded systems.
Author: Hubert Kaeslin
Publisher: Morgan Kaufmann
ISBN: 0128007729
Category : Technology & Engineering
Languages : en
Pages : 599
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Book Description
Top-Down VLSI Design: From Architectures to Gate-Level Circuits and FPGAs represents a unique approach to learning digital design. Developed from more than 20 years teaching circuit design, Doctor Kaeslin's approach follows the natural VLSI design flow and makes circuit design accessible for professionals with a background in systems engineering or digital signal processing. It begins with hardware architecture and promotes a system-level view, first considering the type of intended application and letting that guide your design choices. Doctor Kaeslin presents modern considerations for handling circuit complexity, throughput, and energy efficiency while preserving functionality. The book focuses on application-specific integrated circuits (ASICs), which along with FPGAs are increasingly used to develop products with applications in telecommunications, IT security, biomedical, automotive, and computer vision industries. Topics include field-programmable logic, algorithms, verification, modeling hardware, synchronous clocking, and more. - Demonstrates a top-down approach to digital VLSI design. - Provides a systematic overview of architecture optimization techniques. - Features a chapter on field-programmable logic devices, their technologies and architectures. - Includes checklists, hints, and warnings for various design situations. - Emphasizes design flows that do not overlook important action items and which include alternative options when planning the development of microelectronic circuits.
Author: Hamilton B. Carter
Publisher: Springer Science & Business Media
ISBN: 038738152X
Category : Technology & Engineering
Languages : en
Pages : 366
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Book Description
The purpose of the book is to train verification engineers on the breadth of technologies available and to give them a utilitarian methodology for making effective use of those technologies. The book is easy to understand and a joy to read. Its organization follows a ‘typical’ verification project from inception to completion, (planning to closure). The book elucidates concepts using non-technical terms and clear entertaining explanations. Analogies to other fields are employed to keep the book light-hearted and interesting.
