Author: David A. Wood
Publisher:
ISBN:
Category : Cache memory
Languages : en
Pages : 524
Book Description
The Design and Evaluation of In-cache Address Translation
Author: David A. Wood
Publisher:
ISBN:
Category : Cache memory
Languages : en
Pages : 524
Book Description
Publisher:
ISBN:
Category : Cache memory
Languages : en
Pages : 524
Book Description
Reducing Address Translation Overheads with Virtual Caching
Author: Hongil Yoon
Publisher:
ISBN:
Category :
Languages : en
Pages : 126
Book Description
This dissertation research addresses overheads in supporting virtual memory, especially virtual-to-physical address translation overheads (i.e., performance, power, and energy) via a Translation Lookaside Buffer (TLB). To overcome the overheads, we revisit virtually indexed, virtually tagged caches. In practice, they have not been common in commercial microarchitecture designs, and the crux of the problem is the complications of dealing with virtual address synonyms. This thesis makes novel, empirical observations, based on real world applications, that show temporal properties of synonym accesses. By exploiting these observations, we propose a practical virtual cache design with dynamic synonym remapping (VC-DSR), which effectively reduces the design complications of virtual caches. The proposed approach (1) dynamically decides a unique virtual page number for all the synonymous virtual pages that map to the same physical page and (2) uses this unique page number to place and look up data in the virtual caches, while data from the physical page resides in the virtual caches. Accesses to this unique page number proceed without any intervention. Accesses to other synonymous pages are dynamically detected, and remapped to the corresponding unique virtual page number to correctly access data in the cache. Such remapping operations are rare, due to the temporal properties of synonyms, allowing our proposal to achieve most of the benefits (i.e., performance, power, and energy) of virtual caches, without software involvement. We evaluate the effectiveness of the proposed virtual cache design by integrating it into modern CPUs as well as GPUs in heterogeneous systems. For the proposed L1 virtual cache of CPUs, the experimental results show that our proposal saves about 92% of dynamic energy consumption for TLB lookups and achieves most of the latency benefit (about 99.4%) of ideal (but impractical) virtual caches. For the proposed entire GPU virtual cache hierarchy, we see an average of 77% performance benefits over the conventional GPU MMU.
Publisher:
ISBN:
Category :
Languages : en
Pages : 126
Book Description
This dissertation research addresses overheads in supporting virtual memory, especially virtual-to-physical address translation overheads (i.e., performance, power, and energy) via a Translation Lookaside Buffer (TLB). To overcome the overheads, we revisit virtually indexed, virtually tagged caches. In practice, they have not been common in commercial microarchitecture designs, and the crux of the problem is the complications of dealing with virtual address synonyms. This thesis makes novel, empirical observations, based on real world applications, that show temporal properties of synonym accesses. By exploiting these observations, we propose a practical virtual cache design with dynamic synonym remapping (VC-DSR), which effectively reduces the design complications of virtual caches. The proposed approach (1) dynamically decides a unique virtual page number for all the synonymous virtual pages that map to the same physical page and (2) uses this unique page number to place and look up data in the virtual caches, while data from the physical page resides in the virtual caches. Accesses to this unique page number proceed without any intervention. Accesses to other synonymous pages are dynamically detected, and remapped to the corresponding unique virtual page number to correctly access data in the cache. Such remapping operations are rare, due to the temporal properties of synonyms, allowing our proposal to achieve most of the benefits (i.e., performance, power, and energy) of virtual caches, without software involvement. We evaluate the effectiveness of the proposed virtual cache design by integrating it into modern CPUs as well as GPUs in heterogeneous systems. For the proposed L1 virtual cache of CPUs, the experimental results show that our proposal saves about 92% of dynamic energy consumption for TLB lookups and achieves most of the latency benefit (about 99.4%) of ideal (but impractical) virtual caches. For the proposed entire GPU virtual cache hierarchy, we see an average of 77% performance benefits over the conventional GPU MMU.
Report
Author:
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 478
Book Description
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 478
Book Description
Design and Evaluation of the SPUR Lisp Architecture
Author: George Sabin Taylor
Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 356
Book Description
Publisher:
ISBN:
Category : Dissertations, Academic
Languages : en
Pages : 356
Book Description
Proceedings
Author:
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 344
Book Description
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 344
Book Description
Computer Sciences Technical Report
Author:
Publisher:
ISBN:
Category : Computers
Languages : en
Pages : 404
Book Description
Publisher:
ISBN:
Category : Computers
Languages : en
Pages : 404
Book Description
Cache and Memory Hierarchy Design
Author: Steven A. Przybylski
Publisher: Morgan Kaufmann
ISBN: 1558601368
Category : Computers
Languages : en
Pages : 1017
Book Description
A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.
Publisher: Morgan Kaufmann
ISBN: 1558601368
Category : Computers
Languages : en
Pages : 1017
Book Description
A widely read and authoritative book for hardware and software designers. This innovative book exposes the characteristics of performance-optimal single- and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution time.
ACM SIGPLAN notices
Author:
Publisher:
ISBN:
Category : Programming languages (Electronic computers)
Languages : en
Pages : 812
Book Description
Publisher:
ISBN:
Category : Programming languages (Electronic computers)
Languages : en
Pages : 812
Book Description
Third International Symposium on High-Performance Computer Architecture
Author:
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
ISBN: 9780818677649
Category : Computers
Languages : en
Pages : 372
Book Description
Publisher: Institute of Electrical & Electronics Engineers(IEEE)
ISBN: 9780818677649
Category : Computers
Languages : en
Pages : 372
Book Description
Reliable Computer Systems
Author: Daniel P. Siewiorek
Publisher: CRC Press
ISBN: 1439863962
Category : Computers
Languages : en
Pages : 908
Book Description
This classic reference work is a comprehensive guide to the design, evaluation, and use of reliable computer systems. It includes case studies of reliable systems from manufacturers, such as Tandem, Stratus, IBM, and Digital. It covers special systems such as the Galileo Orbiter fault protection system and AT&T telephone switching system processors
Publisher: CRC Press
ISBN: 1439863962
Category : Computers
Languages : en
Pages : 908
Book Description
This classic reference work is a comprehensive guide to the design, evaluation, and use of reliable computer systems. It includes case studies of reliable systems from manufacturers, such as Tandem, Stratus, IBM, and Digital. It covers special systems such as the Galileo Orbiter fault protection system and AT&T telephone switching system processors