Test generation techniques for sequential circuits PDF Download
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Author: Nikolaus Gouders
Publisher:
ISBN:
Category :
Languages : en
Pages : 6
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Book Description
Author: Nikolaus Gouders
Publisher:
ISBN:
Category :
Languages : en
Pages : 6
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Book Description
Author: Xiaoming Yu
Publisher:
ISBN:
Category :
Languages : en
Pages : 214
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Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
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Author: Thomas E. Marchok
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 138
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Book Description
Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."
Author: G. Russell
Publisher: Springer Science & Business Media
ISBN: 9780747600015
Category : Computers
Languages : en
Pages : 406
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Author: N. K. Jha
Publisher: Cambridge University Press
ISBN: 9780521773560
Category : Computers
Languages : en
Pages : 1016
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Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide-ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through every key area, including detailed treatment of the latest techniques such as system-on-a-chip and IDDQ testing. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Author: Venkat N. Koripalli
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
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Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
Author: Yong Chang Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 172
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Author: Thomas Michael Niermann
Publisher:
ISBN:
Category :
Languages : en
Pages : 212
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Book Description
Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a complete scan design methodology can be prohibitive in both area overhead and performance degradation. Therefore, an efficient sequential circuit test generation system which generates tests for all detectable faults and identifies all untestable faults in the original design is necessary. The information on untestable faults could be used to add minimal design for test hardware to make these faults testable. This thesis presents several new techniques to improve the performance of sequential circuit test generators. Among the concepts presented are unnecessary state elimination, and the use of fault simulation knowledge to increase test coverage during a second phase of test generation, a targeted D element technique for D propagation, and the use of the good circuit state knowledge. The concepts presented in the thesis were implemented and tested on the ISCAS sequential benchmark circuits. This thesis presents an improved fault simulation algorithm based on a combination of the parallel, concurrent and differential fault simulation algorithms. This fault simulator is shown to require much less memory while being 6 to 67 times faster than a traditional concurrent fault simulator.
Author: Thiep V. Nguyen
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
The Boolean difference is a mathematical concept which has proved its usefulness in the study of single and multiple stuck-at faults in combinational circuits. This tool of analysis was extended to cover multiple stuck-at faults in synchronous sequential circuits as well. In this dissertation, modifications to previous work are presented, together with the development of a new method for deriving the required shortest test sequence to detect a specified multiple fault. First, the vector Boolean difference technique is utilized to determine the input vector that will produce a difference in output between the fault-free and faulty circuits with both starting in the same initial state. If that detection cannot be achieved immediately, then the state transition matrices of both circuits are combined and used to form a matrix of detecting state pairs. Each of these pairs comprises of the present states of both circuits for which an output difference will be detected by an input vector. The detecting tree is then built leading the two circuits from the same initial state to the first detecting state found to complete the search for the shortest test sequence. Besides being able to identify, at an early stage, faults that are undetectable, this algorithm guarantees the generation of a shortest test sequence, if one exists, for every multiple stuck-at fault in a synchronous sequential circuit having a synchronizing sequence or a known initial state. A computer program was also written as a tool to automatically generate test sequences for detecting single or multiple faults in both combinational and synchronous sequential circuits.
