Test Generation and Test Application Time Reduction for Sequential Circuits PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Test Generation and Test Application Time Reduction for Sequential Circuits PDF full book. Access full book title Test Generation and Test Application Time Reduction for Sequential Circuits by Soo Y. Lee. Download full books in PDF and EPUB format.
Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
Get Book Here
Book Description
Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
Get Book Here
Book Description
Author: Gyoochan Sim
Publisher:
ISBN:
Category :
Languages : en
Pages : 80
Get Book Here
Book Description
Author: Yong Chang Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 172
Get Book Here
Book Description
Author: Ernest Aubert Carter
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 342
Get Book Here
Book Description
Author: Thomas E. Marchok
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 138
Get Book Here
Book Description
Abstract: "Several manufacturing challenges have accompanied the explosive growth in the scale of integration for VLSI circuits. One of these is the increased difficulty of generating manufacturing test sets, which has resulted from the vast increase in the ratio of the number of transistors to the number of I/O pins. The difficulty of test generation is crucial since it impacts both the resultant product quality and time to market, both of which continue to gain importance in the present day semiconductor industry. Design for testability (DFT) techniques can be used to offset this difficulty. The mechanics of such techniques are well understood. DFT techniques are also known to increase other manufacturing costs and to decrease performance. Thus the relevant issue facing designers is not how to use DFT, but rather if such techniques should be applied. The correct decision is a matter of economics. Integrated circuit (IC) designers must balance manufacturing costs, performance, time to market, and product quality concerns. Achieving the desired balance requires the ability to quantify trade-offs in the different manufacturing costs which various DFT techniques would affect. Unfortunately, test generation cost is among the least predictable of these affected costs, even though the principal reason that DFT techniques are often applied is to reduce the difficulty of test generation. Furthermore, there does not exist a complete understanding of which circuit attributes influence the difficulty of test generation. In this thesis, a model is developed which predicts the difficulty of automatic test generation for non-scan sequential circuits. This model is based on a newly recognized circuit attribute, termed density of encoding, which differs from those notions which have been used to describe this difficulty in the past. This thesis also discusses how the concept of the density of encoding can be applied to devise more powerful sequential automatic test pattern generation algorithms, more efficient DFT techniques, and more effective synthesis for testability schemes."
Author: G. Russell
Publisher: Springer Science & Business Media
ISBN: 9780747600015
Category : Computers
Languages : en
Pages : 406
Get Book Here
Book Description
Author: Kofi Emmanuel Torku
Publisher:
ISBN:
Category :
Languages : en
Pages : 348
Get Book Here
Book Description
Author: Nikolaus Gouders
Publisher:
ISBN:
Category :
Languages : en
Pages : 6
Get Book Here
Book Description
Author: A. Ghosh
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
Author: Xiaoming Yu
Publisher:
ISBN:
Category :
Languages : en
Pages : 214
Get Book Here
Book Description
