Test Generation and Partial Scan Design for Synchronous Sequential Circuits PDF Download
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Author: Dongho Lee
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 248
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Book Description
Author: Dongho Lee
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 248
Get Book Here
Book Description
Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
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Book Description
Author: Kee Sup Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 386
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Book Description
Author: S. Devadas
Publisher:
ISBN:
Category :
Languages : en
Pages : 11
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Book Description
We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented. (RRH).
Author: Yong Chang Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 172
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Book Description
Author: Chia-Lin Chan
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 92
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Book Description
Author: Marinus Hendrik Konijnenburg
Publisher:
ISBN: 9789090120966
Category :
Languages : en
Pages : 226
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Book Description
Author: Vinod Pagalone
Publisher:
ISBN: 9781109789805
Category :
Languages : en
Pages : 83
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Book Description
In testing sequential circuits with scan chains, the test application time is the main factor that determines the overall cost of testing the circuit. For these circuits, the test application time principally depends on the number flip-flops as well as the number of vectors in the test set. Though test set compaction is one way of reducing test application time, for a significant reduction in testing costs the duration of scan operation has to be reduced. The proposed method achieves this by using limited scan operations where the number of shifts is smaller that the actual length of the scan chain. Thus the compacted test set consists of limited scan operations in places where the scan operation cannot be dropped completely. The method uses an iterative procedure that identifies the vectors that have high fault coverage with minimal shifts in the scan chain.
Author: Louis Scheffer
Publisher: CRC Press
ISBN: 1420007947
Category : Technology & Engineering
Languages : en
Pages : 544
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Book Description
Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.
Author: Venkat N. Koripalli
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
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Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
