Row/column Pattern Sensitive Faults in Random Access Memories PDF Download
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Author: Manoj Franklin
Publisher:
ISBN:
Category :
Languages : en
Pages : 180
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Book Description
Author: Manoj Franklin
Publisher:
ISBN:
Category :
Languages : en
Pages : 180
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Book Description
Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 1475749260
Category : Technology & Engineering
Languages : en
Pages : 317
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Book Description
Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal
Author: R. Dean Adams
Publisher: Springer Science & Business Media
ISBN: 0306479729
Category : Technology & Engineering
Languages : en
Pages : 252
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Book Description
Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.
Author: Kanad Chakraborty
Publisher: Prentice Hall PTR
ISBN:
Category : Computers
Languages : en
Pages : 456
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Book Description
This book deals with primarily with reliable and faul-tolerant circuit design and evaluation techniques for RAMS. It examines both the manufacturing faul-tolerance (e.g. self-repair at the time of manufacturing) and online and field-related fault-tolerance (e.g. error-correction). It talks a lot about important techniques and requirements, and explains what needs to be done and why for each of the techniques.
Author: Parag K. Lala
Publisher: Academic Press
ISBN: 9780124343306
Category : Computers
Languages : en
Pages : 222
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Book Description
An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.
Author:
Publisher:
ISBN:
Category : Computer storage devices
Languages : en
Pages : 1032
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Book Description
Author: Said Hamdioui
Publisher: Springer Science & Business Media
ISBN: 1475767064
Category : Technology & Engineering
Languages : en
Pages : 231
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Book Description
Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.
Author: University of Wisconsin--Madison. Department of Electrical and Computer Engineering
Publisher:
ISBN:
Category : Computer engineering
Languages : en
Pages : 404
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Book Description
Author: Alessandro Birolini
Publisher: Springer
ISBN: 3662542099
Category : Technology & Engineering
Languages : en
Pages : 666
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Book Description
This book shows how to build in and assess reliability, availability, maintainability, and safety (RAMS) of components, equipment, and systems. It presents the state of the art of reliability (RAMS) engineering, in theory & practice, and is based on over 30 years author's experience in this field, half in industry and half as Professor of Reliability Engineering at the ETH, Zurich. The book structure allows rapid access to practical results. Methods & tools are given in a way that they can be tailored to cover different RAMS requirement levels. Thanks to Appendices A6 - A8 the book is mathematically self-contained, and can be used as a textbook or as a desktop reference with a large number of tables (60), figures (210), and examples / exercises^ 10,000 per year since 2013) were the motivation for this final edition, the 13th since 1985, including German editions. Extended and carefully reviewed to improve accuracy, it represents the continuous improvement effort to satisfy reader's needs and confidence. New are an introduction to risk management with structurally new models based on semi-Markov processes & to the concept of mean time to accident, reliability & availability of a k-out-of-n redundancy with arbitrary repair rate for n - k=2, 10 new homework problems, and refinements, in particular, on multiple failure mechanisms, approximate expressions, incomplete coverage, data analysis, and comments on ë, MTBF, MTTF, MTTR, R, PA.
Author: A. J. van de Goor
Publisher: John Wiley & Sons
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 542
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Book Description
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles, is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory
