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Reducing Load Latency in Multi-level Cache Hierarchy

Reducing Load Latency in Multi-level Cache Hierarchy PDF Author: Majid Jalili
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Languages : en
Pages : 0

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Book Description
High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Despite decades of research, reducing load latency is still a top priority to achieve high performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is requested by load instructions. However, data prefetching has shown to be lacking in many situations. I make three observations about modern processors relevant to load latency: (1) the cache hierarchy is getting deeper (L4 is being added) and larger in size, requiring new mechanisms to traverse the memory hierarchy without increasing load latency; (2) core counts are increasing and at the same time applications are exhibiting more complex and diverse access patterns, demanding more and better prefetchers to be adopted; and (3) overall processor utilization in cloud servers is very low (