Row/column Pattern Sensitive Faults in Random Access Memories

Row/column Pattern Sensitive Faults in Random Access Memories PDF Author: Manoj Franklin
Publisher:
ISBN:
Category :
Languages : en
Pages : 180

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Book Description

Row/column Pattern Sensitive Faults in Random Access Memories

Row/column Pattern Sensitive Faults in Random Access Memories PDF Author: Manoj Franklin
Publisher:
ISBN:
Category :
Languages : en
Pages : 180

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Book Description


Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits

Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits PDF Author: M. Bushnell
Publisher: Springer Science & Business Media
ISBN: 0306470403
Category : Technology & Engineering
Languages : en
Pages : 690

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Book Description
The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.

Digital Circuit Testing and Testability

Digital Circuit Testing and Testability PDF Author: Parag K. Lala
Publisher: Academic Press
ISBN: 9780124343306
Category : Computers
Languages : en
Pages : 222

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Book Description
An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.

VLSI Testing

VLSI Testing PDF Author: Stanley Leonard Hurst
Publisher: IET
ISBN: 9780852969014
Category : Computers
Languages : en
Pages : 560

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Book Description
Hurst, an editor at the Microelectronics Journal, analyzes common problems that electronics engineers and circuit designers encounter while testing integrated circuits and the systems in which they are used, and explains a variety of solutions available for overcoming them in both digital and mixed circuits. Among his topics are faults in digital circuits, generating a digital test pattern, signatures and self-tests, structured design for testability, testing structured digital circuits and microprocessors, and financial aspects of testing. The self- contained reference is also suitable as a textbook in a formal course on the subject. Annotation copyrighted by Book News, Inc., Portland, OR

Fault-tolerance and Reliability Techniques for High-density Random-access Memories

Fault-tolerance and Reliability Techniques for High-density Random-access Memories PDF Author: Kanad Chakraborty
Publisher: Prentice Hall PTR
ISBN:
Category : Computers
Languages : en
Pages : 456

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Book Description
This book deals with primarily with reliable and faul-tolerant circuit design and evaluation techniques for RAMS. It examines both the manufacturing faul-tolerance (e.g. self-repair at the time of manufacturing) and online and field-related fault-tolerance (e.g. error-correction). It talks a lot about important techniques and requirements, and explains what needs to be done and why for each of the techniques.

Testing Semiconductor Memories

Testing Semiconductor Memories PDF Author: A. J. van de Goor
Publisher: John Wiley & Sons
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 542

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Book Description
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles, is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits PDF Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 0387465472
Category : Technology & Engineering
Languages : en
Pages : 343

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Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.

High Performance Memory Testing

High Performance Memory Testing PDF Author: R. Dean Adams
Publisher: Springer Science & Business Media
ISBN: 0306479729
Category : Technology & Engineering
Languages : en
Pages : 252

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Book Description
Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

LSI/VLSI Testability Design

LSI/VLSI Testability Design PDF Author: Frank F. Tsui
Publisher: McGraw-Hill Companies
ISBN:
Category : Computers
Languages : en
Pages : 730

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Book Description


Testing Static Random Access Memories

Testing Static Random Access Memories PDF Author: Said Hamdioui
Publisher: Springer Science & Business Media
ISBN: 1475767064
Category : Technology & Engineering
Languages : en
Pages : 231

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Book Description
Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.