Optimization of Purely Semiconducting Carbon Nanotube Complementary Field Effect Transistors

Optimization of Purely Semiconducting Carbon Nanotube Complementary Field Effect Transistors PDF Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :

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Highly Stretchable Field-effect Transistors and Design Rules for Photovoltaics by Semiconducting Single-walled Carbon Nanotubes

Highly Stretchable Field-effect Transistors and Design Rules for Photovoltaics by Semiconducting Single-walled Carbon Nanotubes PDF Author: Meng-Yin Wu
Publisher:
ISBN:
Category :
Languages : en
Pages : 140

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This dissertation demonstrates state-of-the-art deformable field-effect transistors (FETs) and photovoltaics based on high purity polymer-wrapped semiconducting single-walled carbon nanotubes (CNTs). We invent a whole-device buckling technique to fabricate stretchable CNT FETs on elastomeric substrates by incorporating a buckled network of CNT in the channel, a buckled layer of an ion gel as the gate dielectric, and buckled metal films as the electrodes. The FETs maintain an on/off ratio of > 104 and a field-effect mobility of > 5 cm2V-1s-1 up to 90% elongation in single direction, more than 100% biaxial elongation, and uniaxial elongation either parallel or perpendicular to the channel. The performance is stable for at least 10000 stretch-release cycles. Failure analysis shows that the extent of elongation is limited only by the magnitude of the pre-strain used during fabrication. A biaxial stretchable inverter with a stable switching behavior up to more than 100% biaxial elongation is demonstrated. Our work is expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. CNTs are also attractive materials for harvesting light in photovoltaics. A crucial aspect of designing efficient photovoltaic devices using CNTs is minimizing the length scale for the absorption of light (LA) and maximizing the length scale across which excitons diffuse (LD) in fibers and films of these materials. In order to facilitate the optimization of these parameters, we model how LA and LD are affected by CNT bandgap polydispersity, inter-nanotube coupling, film disorder, orientation, and defects. Our models are guided by previous experimental measurements of optical absorption spectra and exciton inter-nanotube transfer rates made on isolated and bundled nanotubes in conjunction with kinetic Monte Carlo simulations. Our results provide criteria for materials selection and the design of efficient CNT-based light harvesting devices, in various architectures.

Overcoming Materials Challenges to Achieve Carbon Nanotube Array Transistors with Current Density Exceeding Si and GaAs

Overcoming Materials Challenges to Achieve Carbon Nanotube Array Transistors with Current Density Exceeding Si and GaAs PDF Author: Gerald Joseph Brady
Publisher:
ISBN:
Category :
Languages : en
Pages : 172

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Single walled carbon nanotubes (SWCNTs) have extraordinarily high current carrying capacity, tunable band gap, and can be solution processed at low temperatures making them an attractive candidate to complement or replace bulk semiconducting materials in next generation electronics. Critical materials roadblocks that have limited the performance of SWCNTs in electronics, however, are 1) the isolation of electronically homogeneous SWCNTs, 2) the hierarchical organization of SWCNT building blocks into organized assemblies, 3) reducing defects and impurities, and 4) making intimate electrical contacts to SWCNT films. Here I will present my progress in harnessing arrays of purely semiconducting SWCNTs as the active channel material for high-performance field-effect transistors (FETs) at short channel lengths (30 - 300 nm) where a majority of the SWCNTs directly span the source-drain channel. Conjugated polymers are used to selectively wrap and separate highly enriched semiconducting SWCNTs from electronically heterogeneous arc-discharge SWCNT powders. The semiconducting SWCNTs dispersed in organic-solvent are then aligned into arrays via a technique we pioneered that exploits solvent spreading and self-assembly of SWCNTs at the water-chloroform interface. Solvent rinsing and thermal annealing treatments are performed on the SWCNT array thin films to remove processing induced contaminants and residual polymer as confirmed by XPS, UV-Vis, and FTIR spectroscopy. The combination of high semiconducting purity, pristine quality achieved through surface treatment, and the ideal microstructure of the SWCNT array enables FETs with 7x higher current density than previous state-of-the-art SWCNT FETs. The saturated on-state current density exceeds Si and GaAs FETs of similar dimensions and off-state current density, which demonstrates the competitive advantage of these SWCNT arrays for logic, wireless communications, biological sensors and other semiconductor electronics technologies.

Carbon-Based Electronics

Carbon-Based Electronics PDF Author: Ashok Srivastava
Publisher: CRC Press
ISBN: 9814613118
Category : Science
Languages : en
Pages : 153

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Book Description
Discovery of one-dimensional material carbon nanotubes in 1991 by the Japanese physicist Dr. Sumio Iijima has resulted in voluminous research in the field of carbon nanotubes for numerous applications, including possible replacement of silicon used in the fabrication of CMOS chips. One interesting feature of carbon nanotubes is that these can be me

Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET)

Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET) PDF Author: Raj, Balwinder
Publisher: IGI Global
ISBN: 1799813959
Category : Technology & Engineering
Languages : en
Pages : 255

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Book Description
With recent advancements in electronics, specifically nanoscale devices, new technologies are being implemented to improve the properties of automated systems. However, conventional materials are failing due to limited mobility, high leakage currents, and power dissipation. To mitigate these challenges, alternative resources are required to advance electronics further into the nanoscale domain. Carbon nanotube field-effect transistors are a potential solution yet lack the information and research to be properly utilized. Major Applications of Carbon Nanotube Field-Effect Transistors (CNTFET) is a collection of innovative research on the methods and applications of converting semiconductor devices from micron technology to nanotechnology. The book provides readers with an updated status on existing CNTs, CNTFETs, and their applications and examines practical applications to minimize short channel effects and power dissipation in nanoscale devices and circuits. While highlighting topics including interconnects, digital circuits, and single-wall CNTs, this book is ideally designed for electrical engineers, electronics engineers, students, researchers, academicians, industry professionals, and practitioners working in nanoscience, nanotechnology, applied physics, and electrical and electronics engineering.

Design, Characterization, and Profile Optimization of Silicon-germanium Complementary Metal-oxide-semiconductor Field Effect Transistors on Silicon-on-sapphire (SOS)

Design, Characterization, and Profile Optimization of Silicon-germanium Complementary Metal-oxide-semiconductor Field Effect Transistors on Silicon-on-sapphire (SOS) PDF Author: Suraj J. Mathew
Publisher:
ISBN:
Category : Bipolar transistors
Languages : en
Pages : 258

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Graphene and Carbon Nanotube Field Effect Transistors

Graphene and Carbon Nanotube Field Effect Transistors PDF Author: Thomas H. Caine
Publisher:
ISBN: 9781613242766
Category : Field-effect transistors
Languages : en
Pages : 0

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Book Description
This book describes initial efforts, as part of the new Strategic Technology Institute (STI) on carbon electronics, to model and simulate the performance of graphene field-effect transistors (FETs) using macroscopic descriptions that are classical for semiconductor devices. It is argued that the underlying physics that differentiates these devices from their normal semiconductor-based counterparts is most clearly revealed by non-computer-intensive descriptions that allow the designer to compare their behaviour with that of their well-studied semiconductor counterparts. Because it admits a reasonable description of both the lateral and vertical field and transport functionality of the FET structure, the gradual-channel approximation is key to this approach.

Nanowelded Carbon Nanotubes

Nanowelded Carbon Nanotubes PDF Author: Changxin Chen
Publisher: Springer Science & Business Media
ISBN: 3642014992
Category : Technology & Engineering
Languages : en
Pages : 115

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This book introduces a novel ultrasonic nanowelding technology of carbon nanotubes (CNTs) to metal electrodes and its application for CNT devices. It will be of interest to graduates, scientists and engineers working on CNTs and related topics.

Efficient Methods for Robust Circuit Design and Performance Optimization for Carbon Nanotube Field Effect Transistors

Efficient Methods for Robust Circuit Design and Performance Optimization for Carbon Nanotube Field Effect Transistors PDF Author:
Publisher:
ISBN:
Category : Carbon nanotubes
Languages : en
Pages : 124

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We present a capacitance-based Logical Effort (LE) framework to investigate design issues of high-speed and low-power circuit designs implemented by considering specific requirements and challenges of the carbon nanotube field-effect transistor (CNFET) technology. The LE technique is widely recognized as a pedagogical method to quickly estimate and optimize the propagation delay and transition time in CMOS circuits equivalently without performing transient simulations and detailed delay calculations. In this thesis, we propose novel delay models [Pitch-Aware Logical Effort (PALE) and Position-Aware Pitch Factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. Our developed models are correlated with SPICE simulations using different types of gates and circuits with an average error of 3% and 5% for ideal and realistic cases respectively. Our framework is capable of estimating performance more than 100x faster as compared to SPICE simulations methods. Furthermore, using our models (PALE and PAPF), we present an optimization tool to minimize the area and delay product (ADP) of CNFET circuits. We deploy circuit-level techniques (CLT) prior to optimizing the tubes (CNTs) in the logic gates to achieve highly optimized solution with global approach. Finally, we propose more accurate probabilistic model for yield estimation which incorporates the impact of screening effect on the functional yield after the removal of metallic tubes.

Very-large-scale-integration of Complementary Carbon Nanotube Field-effect Transistors

Very-large-scale-integration of Complementary Carbon Nanotube Field-effect Transistors PDF Author: Christian Lee Lau
Publisher:
ISBN:
Category :
Languages : en
Pages : 82

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Book Description
Electronics is approaching a major paradigm shift as silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to (1) fabricate complementary metal–oxide–semiconductor (CMOS) CNFET circuits that integrate both PMOS and NMOS CNFETs and (2) perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated CMOS systems. Here we propose and experimentally demonstrate a comprehensive manufacturing methodology for CNTs, which encompasses a set of original processing and circuit design techniques that are combined to overcome all of these intrinsic CNT challenges (variability, manufacturing defects, and material defects) across full industry-standard large-area substrates. As a demonstration of the feasibility of implementing this manufacturing methodology, we experimentally demonstrate the world’s first microprocessor built from a beyond-silicon emerging nanotechnology: RV16X-NANO. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 CMOS CNFETs and is designed and fabricated using industry-standard design flows and processes. This work is a major advance for carbon nanotube-based electronics, and more broadly experimentally validates a promising path towards realizing practical next-generation beyond-silicon electronic systems.