Author: H. G. Shah
Publisher:
ISBN:
Category :
Languages : en
Pages : 72
Book Description
The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Multiple Faults in Combinational Logic
Author: H. G. Shah
Publisher:
ISBN:
Category :
Languages : en
Pages : 72
Book Description
The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Publisher:
ISBN:
Category :
Languages : en
Pages : 72
Book Description
The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author).
Fault Detection for Combinational Logic Under the Multiple Fault Assumption
Author: Patrick Wai-Fai Lam
Publisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 92
Book Description
Publisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 92
Book Description
Adaptive Location of Multiple Faults in Combinational Circuits
Author: Alan Douglas May
Publisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 172
Book Description
Publisher:
ISBN:
Category : Electric circuits
Languages : en
Pages : 172
Book Description
Multiple Fault Analysis in Combinational Logic Circuits
Author: Francisco Jose de Oliveira Dias
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 364
Book Description
Publisher:
ISBN:
Category : Digital electronics
Languages : en
Pages : 364
Book Description
Multiple Fault Detection in Combinational Circuits
Author: Sivanarayana Mallela
Publisher:
ISBN:
Category :
Languages : en
Pages : 128
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 128
Book Description
Test generation and fault diagnosis for multiple faults in combinational circuits
Author: Stanford University. Computer Systems Laboratory
Publisher:
ISBN:
Category : Electric fault location
Languages : en
Pages : 52
Book Description
Publisher:
ISBN:
Category : Electric fault location
Languages : en
Pages : 52
Book Description
Multiple Fault Diagnosis in Combinational Networks
Author: Charles Wei-Yuan Cha
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Publisher:
ISBN:
Category :
Languages : en
Pages : 114
Book Description
A new concept, the prime fault, is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime faults as its only components. The use of prime faults greatly simplifies multiple fault analysis and test generation.
Digital Circuit Testing and Testability
Author: Parag K. Lala
Publisher: Academic Press
ISBN: 9780124343306
Category : Computers
Languages : en
Pages : 222
Book Description
An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.
Publisher: Academic Press
ISBN: 9780124343306
Category : Computers
Languages : en
Pages : 222
Book Description
An easy to use introduction to the practices and techniques in the field of digital circuit testing. Lala writes in a user-friendly and tutorial style, making the book easy to read, even for the newcomer to fault-tolerant system design. Each informative chapter is self-contained, with little or no previous knowledge of a topic assumed. Extensive references follow each chapter.
Automated Multiple Fault Test Generation for Combinational Networks
Author: Robert A. Hendrix
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
Book Description
This report deals with multiple fault detection in combinational logic networks; the faults considered are those which may be represented by one or more lines stuck at logic value 0 or 1. Some new theorems and rules are presented which aid in the identification of masking faults, and an algorithm is developed which produces multiple fault detection test sets for single-output combinational logic networks. The algorithm uses a path sensitizing technique to generate tests for members of a set of prime faults; any network fault can be represented by a combination of faults from the prime fault set, and a test which detects all combinations of prime faults will detect any single or multiple fault in the network. A modified version of the algorithm is implemented in the FORTRAN computer programming language; the automated version produces test sets which are optimal or near-optimal and usually complete. In the test generation process, certain redundancies are also detected.
Fault Diagnosis of Multiple Output Combinational Logic Networks
Author: Heramb Singh
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description