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Languages : en
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Author: H. Ebbesen
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Author: Walter Gross
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Languages : en
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Author: H. Ebbesen
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Category :
Languages : en
Pages : 212
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Author: Eoin Carey
Publisher: Springer Science & Business Media
ISBN: 0387236651
Category : Technology & Engineering
Languages : en
Pages : 288
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Book Description
Millimeter-Wave Integrated Circuits delivers a detailed overview of MMIC design, specifically focusing on designs for the millimeter-wave (mm-wave) frequency range. The scope of the book is broad, spanning detailed discussions of high-frequency materials and technologies, high-frequency devices, and the design of high-frequency circuits. The design material is supplemented as appropriate by theoretical analyses. The broad scope of the book gives the reader a good theoretical and practical understanding of mm-wave circuit design. It is best-suited for both undergraduate students who are reading or studying high frequency circuit design and postgraduate students who are specializing in the mm-wave field.
Author: Hao Wang
Publisher:
ISBN: 9781658416467
Category :
Languages : en
Pages :
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The goal of dissertation is to explore feasibility of designing millimeter-wave (mmWave) circuits in CMOS technology, especially when frequency is close to the maximum oscillation frequency f[subscript max] of the active device. In this dissertation, an embedding network method is proposed to design high efficiency fundamental oscillators and high gain amplifier. First, it reports an approach to designing compact high efficiency mmWave fundamental oscillators operating above the f[subscript max]/2 of the active device. The approach takes full consideration of the nonlinearity of the active device and the finite quality factor of the passive devices to provide an accurate and optimal oscillator design in terms of the output power and efficiency. 213-GHz single-ended and differential fundamental oscillators in 65-nm CMOS technology are presented to demonstrate the effectiveness of the proposed method. Using a compact capacitive transformer design, the single-ended oscillator achieves 0.79-mW output power per transistor (16 [mu]m) at 1.0-V supply and a peak dc-to-RF efficiency of 8.02% (V[subscript DD]=0.80 V) within a core area of 0.0101 mm2, and the measured phase noise is −93.4 dBc/Hz at 1-MHz offset. The differential oscillator exhibits approximately the same performance. A 213-GHz fundamental voltage-controlled oscillator (VCO) with bulk tuning method is also developed in this work. The measured peak efficiency of the VCO is 6.02% with a tuning rang of 2.3% at 0.6-V supply.In order to further improve dc-to-RF efficiency, an optimization-based design methodology is then proposed for high-power and high-efficiency mmWave fundamental oscillators in CMOS technology. The optimization is formulated to take into account the loss of the passive components to result in an optimal circuit design. The proposed approach can produce the final design in a single pass of optimization with a fast and robust convergence profile. A comparative study between the T - and the [pi]-embedding networks is presented. It shows that T -embedding is superior to [pi]-embedding in terms of flexibility in biasing and sensitivity to component Q. A design example of a 215-GHz fundamental oscillator in a 65-nm CMOS technology is presented to demonstrate the effectiveness of the proposed design approach. The oscillator achieves 5.17-dBm peak output power at 1.2-V supply with a corresponding dc-to-RF efficiency 12.3% and a peak efficiency of 13.7%. The measured phase noise is −90.0 dBc/Hz and −116.2 dBc/Hz at 1 MHz and 10 MHz offset, respectively. Lastly, embedding network theory is presented to design high gain amplifier in this dissertation. Two embedding theories, constant GC/U and G[subscript max]/GC, are proposed. A 210-GHz high gain amplifier example is designed. Two 16 [mu]m NMOS transistors consist of a differential circuit with V[subscript DD] = 1.2 V and VG = 0.45 V. The total dc power of the designed 210-GHz amplifier is 12.8 mW. The simulated Gain S21 is 16.66 dB. NF is 7.38 dB. Stability factor k is 3.82 at 210 GHz. The simulated 1dB compression point P1dB, input referred third-order intercept point, IIP3 is -22.33 dB, and -12.97 dB, respectively. These simulated results demonstrate the effectiveness of the proposed design theory.
Author: Kenneth J. Button
Publisher: Elsevier
ISBN: 032315669X
Category : Technology & Engineering
Languages : en
Pages : 302
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Book Description
Infrared and Millimeter Waves, Volume 15: Millimeter Components and Techniques, Part VI is concerned with millimeter-wave guided propagation and integrated circuits. This book covers low-noise receiver technology for near-millimeter wavelengths; dielectric image-line antennas; EHF satellite communications (SATCOM) terminal antennas; and semiconductor antennas for millimeter-wave integrated circuits. A scanning airborne radiometer for 30 and 90 GHz and a self-oscillating mixer are also described. This monograph is comprised of six chapters and begins with a discussion on the design of low-noise receivers, with emphasis on problems encountered at near-millimeter wavelengths. Optimization of the material parameters and device topology for both Schottky-barrier diodes and superconducting mixer elements are considered. Some representative examples of state-of-the-art mixers and receivers, designed to operate at frequencies of 100-1000 GHz, are given in order to illustrate the way in which practical, high-performance millimeter-wave devices can be constructed. The following chapters focus on a scanning airborne radiometer for 30 and 90 GHz; a self-oscillating mixer; dielectric image-line antennas; and EHF SATCOM terminal antennas. The final chapter is devoted to semiconductor dipole antennas for millimeter-wave sensors, with particular reference to the basic concepts leading to the development of semiconductor dipoles. A theoretical formulation for tubular semiconductor dipoles is outlined and numerical results are presented to assess their characteristics. This text will be a valuable resource for physicists and electronics and electrical engineers.
Author: Shanthi S. Bhagavatheeswaran
Publisher:
ISBN:
Category : Metal oxide semiconductors, Complementary
Languages : en
Pages : 234
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The Local Oscillator (LO) signal is used for frequency translation and channel selection in a transceiver. The frequency of the LO is maintained constant by a Phase-Locked Loop (PLL). This dissertation demonstrates a technique for the on-chip integration of millimeter-wave (mm-Wave) PLL in Complementary Metal-Oxide Semiconductor (CMOS) using sub-harmonic injection locking, wherein a low-frequency PLL drives an injection locked oscillator (ILO) operating at a higher harmonic. This simplifies the divider design in the PLL and achieves lower power consumption. Traditionally, sub-TeraHertz (THz) electronics have been designed using III-V semiconductors. With scaling of CMOS technology and consequent increase in their peak-ft and peak-fMAX , coupled with the ease of integration with mixed-signal/digital circuits, there have been recent developments in the mm-Wave and THz circuits in CMOS. Challenges with deep sub-micron CMOS implementation include implementation of passives, operating with lower power supplies, achieving higher output powers for the signal, and achieving good phase noise performance. A 100 GHz ILO is implemented in a commercial 65 nm CMOS process. The design can be adapted to generate other THz frequencies. Measured results of the 100 GHz ILO is shown. The measured self-oscillation frequency of the ILO is 103.81 GHz. This can be tuned using a varactor and/or by changing the tail bias. The measured output frequency range of the ILO is 99.9-103.81 GHz. Phase noise estimated from locked spectrum is -70 dBc/Hz at 10 MHz offset. The power consumption is 12 mW, and area is 0.08 mm 2 . The ILO driven with a sub-harmonic injection locked PLL, in a low power mm-Wave and THz phased-array systems, eliminates the high frequency divider in the PLL and lends itself to easy frequency scaling. PLL parameters for a 100 GHz imaging system using the sub-harmonic injection locked PLL is derived. This topology can lead to significant power reduction in an n x n multi-receiver system: reducing the power by 20 % per receiver, the number of high-frequency PLLs by n2 - 1, and obviates the rail-to-rail routing of multi-GHz local oscillator (LO) signal across the chip. Patterned ground shield inductor fabricated in digital 45 nm CMOS, yielding quality factor improvement at mm-Wave/sub-THz frequencies, is also shown.
