Gate-level Dual-threshold Static Power Optimization Methodology (GDSPOM) for Designing High-speed Low-power SOC Applications Using 90nm MTCMOS Technology PDF Download
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Author: Benjamin Chung
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 102
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Book Description
As integrated-circuits (IC) technology advances into the deep-submicron (DSM) regime, more functionality can be combined onto a single chip. One major challenge in designing such a complex device is to keep the power consumption in check while capitalizing on the highest performance that DSM technology can offer. In this thesis we describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold - high Vt for good standby power and low Vt for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.
Author: Benjamin Chung
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 102
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Book Description
As integrated-circuits (IC) technology advances into the deep-submicron (DSM) regime, more functionality can be combined onto a single chip. One major challenge in designing such a complex device is to keep the power consumption in check while capitalizing on the highest performance that DSM technology can offer. In this thesis we describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold - high Vt for good standby power and low Vt for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.
Author: Johan Vounckx
Publisher: Springer Science & Business Media
ISBN: 3540390944
Category : Computers
Languages : en
Pages : 691
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Book Description
This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.
Author: José Monteiro
Publisher: Springer Science & Business Media
ISBN: 3642118011
Category : Computers
Languages : en
Pages : 380
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Book Description
This book constitutes the thoroughly refereed post-conference proceedings of 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, featuring Integrated Circuit and System Design, held in Delft, The Netherlands during September 9-11, 2009. The 26 revised full papers and 10 revised poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Author: Nadine Azemard
Publisher: Springer Science & Business Media
ISBN: 354074441X
Category : Computers
Languages : en
Pages : 595
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Book Description
This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Author: Harry I-An Chen
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 0
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Book Description
As CMOS System-on-Chips approach the limits of power dissipation, static power has become dominant in a circuit's total power dissipation. The static power is increasing exponentially as technology nodes shrink and is projected to exceed the dynamic power within the near future. Techniques that use the multi-threshold CMOS (MTCMOS) technology have been developed to reduce static power effectively. In this thesis, a novel triple-threshold static power minimization technique in high-level synthesis has been developed using the 90nm MTCMOS technology. Using static timing analysis, the optimal partitioning of gates with three different threshold voltages is determined via iterative analysis. The proposed triple-threshold technique has been applied to optimize several benchmark circuits, and the results show an average saving in static power close to 90% compared to un-optimized LVT designs. For all designs tested, the triple-threshold technique has produced designs with lower static power compared to a dual-threshold technique.
Author: David Flynn
Publisher: Springer Science & Business Media
ISBN: 0387718192
Category : Technology & Engineering
Languages : en
Pages : 303
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Book Description
This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. In addition to providing a theoretical basis for these techniques, the book addresses the practical issues of implementing them in today's designs with today's tools.
Author: Tejas Hadke
Publisher:
ISBN:
Category :
Languages : en
Pages : 138
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Book Description
According to Moore's law, the number of transistors on integrated circuits (ICs) double approximately every two years. Over the years, this growth in number of transistors has reached to billions of transistors per IC, operating at very high frequencies. However, there are many factors limiting this growth rate including power consumption of high-density high-speed integrated circuits. Various techniques have evolved offering reduction in dynamic power consumption and leakage power. Traditional methods like use of power efficient circuits, parallelism in micro-architectures, along with nontraditional methods such as clock gating, variable supply voltage and frequency scaling are becoming significantly important in lowering dynamic power consumption. The leakage power, which has become more significant in the recent high-density designs, can be reduced by minimizing usage of low threshold voltage cells, adding power gating, back biasing, reducing oxide thickness, and using new devices such as FINFET's. Design engineers have to consider clock and power gating techniques up front in the design cycle in today's multi-threshold, multi-oxide, multi-voltage and multi-clock devices. Understanding and implementing power intent at register transfer level (RTL), netlist and PG netlist stages requires additional design verification efforts. In this project, several power reduction and management techniques were studied and applied to an existing System on Chip (SoC) system consisting of an ARM processor, an Ethernet controller, and a DDR controller. Clock and Multi VDD power gating were considered as primary techniques for achieving power reduction. Power intent was created as per the IEEE 1801-2009 Unified Power Format standard. Open source Verilog model of the SoC ARM processor was used as a reference model, along with Synopsys® 90 nm cell library. Synopsys® Electronic Design Automation (EDA) tools were utilized in carrying out simulation, synthesis, and power analysis phases of the project. In addition to implementation of low-power RTL design techniques, use of clock gating, power gating, multi-voltage design partition and multi-threshold voltage cells showed significant improvement in power consumption of the System on Chip (SoC) system used in this work. By considering design issues and verification requirements of these techniques, we developed a power-aware SoC design flow. This enhanced methodology presents a unique approach for effectively incorporating low-power techniques early in the design phase.
Author: Emeshaw Ashenafi
Publisher:
ISBN:
Category : Electronic dissertations
Languages : en
Pages : 164
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Book Description
Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.
Author: Feng Gao
Publisher:
ISBN:
Category :
Languages : en
Pages : 308
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Book Description
Author: Priyanka K
Publisher:
ISBN: 9783330060654
Category :
Languages : en
Pages : 104
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Book Description
