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Author: Carlos Delgado Kloos
Publisher: Springer Science & Business Media
ISBN: 1461522374
Category : Technology & Engineering
Languages : en
Pages : 263
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Book Description
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
Author: Carlos Delgado Kloos
Publisher: Springer Science & Business Media
ISBN: 1461522374
Category : Technology & Engineering
Languages : en
Pages : 263
Get Book Here
Book Description
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several tools, both commercial and academic. If different tools and users are to generate and read the same language then it is necessary that the same semantics is assigned by them to all constructs and elements of the language. The current IEEE standard VHDL language reference manual (LRM) tries to define VHDL as well as possible in a descriptive way, explaining the semantics in English. But rigor and clarity are very hard to maintain in a semantics defined in this way, and that has already given rise to many misconceptions and contradictory interpretations. Formal Semantics for VHDL is the first book that puts forward a cohesive set of semantics for the VHDL language. The chapters describe several semantics each based on a different underlying formalism: two of them use Petri nets as target language, and two of them higher order logic. Two use functional concepts, and finally another uses the concept of evolving algebras. Formal Semantics for VHDL is essential reading for researchers in formal methods and can be used as a text for an advanced course on the subject.
Author: Kothanda Umamageswaran
Publisher: Springer Science & Business Media
ISBN: 1461551234
Category : Technology & Engineering
Languages : en
Pages : 169
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Book Description
Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
Author: Kothanda Umamageswaran
Publisher:
ISBN: 9781461551249
Category :
Languages : en
Pages : 184
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Book Description
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
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Book Description
Author: National Aeronautics and Space Adm Nasa
Publisher:
ISBN: 9781730910920
Category :
Languages : en
Pages : 78
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Book Description
In the first part of the report, we give a detailed description of an operational semantics for a large subset of VHDL, the VHSIC Hardware Description Language. The semantics is written in the functional language Caliban, similar to Haskell, used by the theorem prover Clio. We also describe a translator from VHDL into Caliban semantics and give some examples of its use. In the second part of the report, we describe our experience in using the VHDL semantics to try to verify a large VHDL design. We were not able to complete the verification due to certain complexities of VHDL which we discuss. We propose a VHDL verification method that addresses the problems we encountered but which builds on the operational semantics described in the first part of the report. Bickford, Mark Unspecified Center...
Author: Dirk Eisenbiegler
Publisher:
ISBN:
Category :
Languages : en
Pages : 92
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Book Description
Author: Subash Shankar
Publisher:
ISBN:
Category :
Languages : en
Pages : 326
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Book Description
Author: Wolfgang Grieskamp
Publisher: Springer Science & Business Media
ISBN: 3540411968
Category : Computers
Languages : en
Pages : 449
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Book Description
This book constitutes the refereed proceedings of the Second International Conference on Integrated Formal Methods, IFM 2000, held in Dagstuhl, Germany in November 2000. The 22 revised full papers presented together with the abstracts of two invited talks were carefully reviewed and selected from 58 submissions. The papers are grouped together in topical sections on linking and extending notations, methodology, foundation of one formalism by another, semantics, and verification and validation.
Author: Carlos Delgado Kloos
Publisher: Springer Science & Business Media
ISBN: 3642606415
Category : Computers
Languages : en
Pages : 304
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Book Description
Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.
Author: Max Fuchs
Publisher:
ISBN:
Category : VHDL (Computer hardware description language)
Languages : en
Pages : 31
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Book Description
Abstract: "This tutorial paper gives a functional semantics for delta-delay VHDL, i.e. VHDL restricted to zero-delay signal assignments. In combination with the sequential statements zero-delay signal assignment is sufficient to generate the full algorithmic expressibility of VHDL. The restriction is useful for a formal semantics of VHDL aimed at higher levels of abstraction where real, absolute, and precise timing often is painful if not impossible to prescribe. The approach employs the functional specification methodology FOCUS which is based on the concept of streams and stream-processing functions. It advocates a three-level semantics reflecting VHDL's three syntactic levels of expressions, statements, and processes."
