Author: Scott E. Chilstedt
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
The ITRS (International Technology Roadmap for Semiconductors) has recommended that carbon-based transistors be given further study as a potential 0́−Beyond CMOS0́+ technology. Unlike traditional devices with a silicon channel, these transistors have channels made from semiconducting carbon nanomaterials in the form of carbon nanotubes (CNTs) and graphene nanoribbons (GNRs). The research community has given specific attention to these two carbon allotropes because of their outstanding electrical properties, including high mobilities at room temperature, high current densities, and micron-scale mean free paths. Carbon nanomaterial transistors offer many opportunities for circuits and systems, but also present a number of challenges in terms of fabrication, architecture design, and CAD integration. In order to be useful to the semiconductor industry, transistors must be connected together to form higher order circuits. Due to the increased variation and defects in nanometer-scale fabrication, and the regular nature of bottom-up self-assembly, field programmable devices are a promising initial application for such technologies. This thesis details the design and evaluation of a carbon nanomaterial based architecture called FPCNA (field programmable carbon nanotube array). Nanomaterial based devices and circuit building blocks are developed and characterized, including a lookup table created entirely from continuous CNT arrays. To determine the performance of these building blocks, variation-aware physical design tools are used, with statistical timing analysis that can handle both Gaussian and non-Gaussian random variables. When the FPCNA architecture is evaluated using this CAD flow, a 2.75©7 performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5.07©7 footprint reduction compared to the baseline FPGA.
Author: Chen Dong
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
FPGAs (field programmable gate arrays) are attractive alternatives compared to ASICs (application-specific integrated circuits) for significantly lowering amortized manufacturing costs and dramatically improving design productivity. The architecture of an FPGA is very regular. It is relatively easy to design a highly optimized tile, with consideration of various manufacturing related issues, and then to replicate it many times across the chip. The configurability of FPGAs also enables yield improvement and defect tolerance. However, FPGAs are still facing serious challenges in terms of delay, power consumption, and logic density compared to ASICs. FPGA is estimated to be over twenty times less efficient in logic density, over three times worse in delay, and over ten times higher in power consumption compared to a functionally equivalent ASIC. One promising way to improve FPGA performance is to incorporate three-dimensional (3D) integration, which increases the number of active layers and optimizes the interconnect network vertically. Another solution is to apply novel nanoelectronic materials (nanomaterials) and devices. This dissertation introduces three novel reconfigurable architectures, named 3D nFPGA, FPCNA (field programmable carbon nanotube array), and NEM FPGA (nanoelectromechanical FPGA), which utilize 3D integration techniques and new nanoscale materials synergistically. Customized CAD flows that consider process variation have been developed for different architectures to evaluate their potential performances. Also described is a 3D variation aware routing flow, which is an essential tool for future 3D FPGA architecture exploration. 3D nFPGA is based on CMOS (complementary metal-oxide-semiconductor) and nano hybrid techniques that incorporate nanomaterials such as nanowire crossbars and carbon nanotube bundles into the CMOS fabrication process. Using unique features of FPGAs and a novel 3D stacking method enabled by the application of nanomaterials, 3D nFPGA obtains a 4©7 footprint reduction comparing to the traditional CMOS-based 2D FPGAs. The performance and power of 3D nFPGA driven by the 20 largest MCNC (microelectronics center of North Carolina) benchmarks have been evaluated. Results demonstrate that 3D nFPGA is able to provide a performance gain of 2.6©7 with a small power overhead compared to the traditional 2D FPGA. FPCNA includes lookup tables created entirely from continuous carbon nanotube (CNT) ribbons. To determine the performance of the building blocks, variation aware physical design tools are used, with statistical static timing analysis (SSTA) that can handle both Gaussian and non-Gaussian random variables. A 2.75©7 performance improvement is seen over an equivalent CMOS FPGA at a 95% yield. In addition, FPCNA offers a 5©7 footprint reduction compared to a baseline FPGA. 3D NEM FPGA is the architecture that utilizes nanoelectromechanical (NEM) relays and 3D integration techniques synergistically. This proposed architecture has unique features including a hybrid CMOS-NEM FPGA lookup table (LUT) and configurable logic block (CLB), NEM-based switch block (SB) and connection block (CB), and face-to-face 3D stacking. This architecture also has a built-in feature called direct link, which takes advantage of the short vertical wire length provided by 3D stacking to further enhance performance. An overall 46.3% critical path delay reduction has been observed compared to its CMOS counterpart. To maximize the potential performance gain of 3D integrated circuit architectures, an SSTA engine was developed to deal with both uncorrelated and correlated variations in 3D FPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physical design tool TPR as a base, a new 3D routing algorithm is developed, which improves the average performance of two-layer designs by over 22% and three-layer designs by over 27%.
Author: Albert Lin
Publisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 166
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Book Description
Carbon Nanotube Field Effect Transistor (CNFET) technology has received a lot of attention in the past few years as a promising extension to silicon-CMOS for future digital logic integrated circuits. While recent research has advanced CNFET technology past many important milestones, robust and scalable solutions must be developed to realize the full potential of CNFETs. Thus, this thesis aims to develop a suite of techniques, spanning from material synthesis to circuit solutions, compatible with very-large-scale integration (VLSI). Specifically, to enable the real-world engineering of carbon nanotube integrated circuits, this thesis presents (1) wafer-scale aligned CNT growth, (2) wafer-scale CNT Transfer, (3) wafer-scale device and circuit fabrication techniques, and (4) ACCNT, a VLSI-compatible circuit design solution to surmounting the problem of metallic CNTs. These techniques culminated in the successful demonstration of CNT transistors, inverters, and NAND logic gates on a wafer scale. Furthermore, this thesis sheds light on important design considerations for the demonstration of a simple CNT "computer" and suggests a few critical directions for future work in the field of carbon nanotube technology. In contributing the above, this thesis hopes to propel carbon nanotube technology forward towards the vision of robust, large-scale integrated circuits using high-density carbon nanotubes.
Author: Aida Todri-Sanial
Publisher: Springer
ISBN: 3319297465
Category : Technology & Engineering
Languages : en
Pages : 340
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Book Description
This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits.
Author: P. Uma Sathyakam
Publisher: Springer Nature
ISBN: 9811588880
Category : Technology & Engineering
Languages : en
Pages : 134
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Book Description
This book provides a single-source reference on carbon nanotubes for interconnect applications. It presents the recent advances in modelling and challenges of carbon nanotube (CNT)-based VLSI interconnects. Starting with a background of carbon nanotubes and interconnects, this book details various aspects of CNT interconnect models, the design metrics of CNT interconnects, crosstalk analysis of recently proposed CNT interconnect structures, and geometries. Various topics covered include the use of semiconducting CNTs around metallic CNTs, CNT interconnects with air gaps, use of emerging ultra low-k materials and their integration with CNT interconnects, and geometry-based crosstalk reduction techniques. This book will be useful for researchers and design engineers working on carbon nanotubes for interconnects for both 2D and 3D integrated circuits.
Author: Niraj K. Jha
Publisher: Springer Science & Business Media
ISBN: 1441976094
Category : Technology & Engineering
Languages : en
Pages : 489
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Book Description
This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS. While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.
Author: David Crawley
Publisher: CRC Press
ISBN: 1420034782
Category : Computers
Languages : en
Pages : 345
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Book Description
It is becoming increasingly clear that the two-dimensional layout of devices on computer chips hinders the development of high-performance computer systems. Three-dimensional structures will be needed to provide the performance required to implement computationally intensive tasks. 3-D Nanoelectronic Computer Architecture and Implementation reviews the state of the art in nanoelectronic device design and fabrication and discusses the architectural aspects of 3-D designs, including the possible use of molecular wiring and carbon nanotube interconnections. This is a valuable reference for those involved in the design and development of nanoelectronic devices and technology.
Author: Ali Javey
Publisher: Springer Science & Business Media
ISBN: 0387692851
Category : Technology & Engineering
Languages : en
Pages : 275
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Book Description
This book provides a complete overview of the field of carbon nanotube electronics. It covers materials and physical properties, synthesis and fabrication processes, devices and circuits, modeling, and finally novel applications of nanotube-based electronics. The book introduces fundamental device physics and circuit concepts of 1-D electronics. At the same time it provides specific examples of the state-of-the-art nanotube devices.
Author: Brajesh Kumar Kaushik
Publisher: Springer
ISBN: 8132220471
Category : Technology & Engineering
Languages : en
Pages : 94
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Book Description
The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.
Author: Rohit Sharma
Publisher: CRC Press
ISBN: 1351831593
Category : Technology & Engineering
Languages : en
Pages : 328
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Book Description
Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text: Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs) Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs) Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications Describes large-scale integration testing and state-of-the-art low-power testing solutions Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal–oxide–semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference that not only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.
