Author: F. Lombardi
Publisher: Springer Science & Business Media
ISBN: 9400914172
Category : Technology & Engineering
Languages : en
Pages : 531
Book Description
This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.
Testing and Diagnosis of VLSI and ULSI
Author: F. Lombardi
Publisher: Springer Science & Business Media
ISBN: 9400914172
Category : Technology & Engineering
Languages : en
Pages : 531
Book Description
This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.
Publisher: Springer Science & Business Media
ISBN: 9400914172
Category : Technology & Engineering
Languages : en
Pages : 531
Book Description
This volume contains a collection of papers presented at the NATO Advanced Study Institute on ·Testing and Diagnosis of VLSI and ULSI" held at Villa Olmo, Como (Italy) June 22 -July 3,1987. High Density technologies such as Very-Large Scale Integration (VLSI), Wafer Scale Integration (WSI) and the not-so-far promises of Ultra-Large Scale Integration (ULSI), have exasperated the problema associated with the testing and diagnosis of these devices and systema. Traditional techniques are fast becoming obsolete due to unique requirements such as limited controllability and observability, increasing execution complexity for test vector generation and high cost of fault simulation, to mention just a few. New approaches are imperative to achieve the highly sought goal of the • three months· turn around cycle time for a state-of-the-art computer chip. The importance of testing and diagnostic processes is of primary importance if costs must be kept at acceptable levels. The objective of this NATO-ASI was to present, analyze and discuss the various facets of testing and diagnosis with respect to both theory and practice. The contents of this volume reflect the diversity of approaches currently available to reduce test and diagnosis time. These approaches are described in a concise, yet clear way by renowned experts of the field. Their contributions are aimed at a wide readership: the uninitiated researcher will find the tutorial chapters very rewarding. The expert wiII be introduced to advanced techniques in a very comprehensive manner.
Records of the 1993 IEEE International Workshop on Memory Testing, August 9-10, 1993, San Jose, California
Author: Rochit Rajsuman
Publisher:
ISBN: 9780818641503
Category : Computer storage devices
Languages : en
Pages : 168
Book Description
From the August 1993 workshop in San Jose, California, 26 papers report the latest findings on testing computer memory. The sections include test pattern generation, algorithms, fault models, testing for process defects and yield improvement, and radiation issues and space applications. No subject i
Publisher:
ISBN: 9780818641503
Category : Computer storage devices
Languages : en
Pages : 168
Book Description
From the August 1993 workshop in San Jose, California, 26 papers report the latest findings on testing computer memory. The sections include test pattern generation, algorithms, fault models, testing for process defects and yield improvement, and radiation issues and space applications. No subject i
IEEE VLSI Test Symposium
Author:
Publisher:
ISBN:
Category : Application-specific integrated circuits
Languages : en
Pages : 498
Book Description
Publisher:
ISBN:
Category : Application-specific integrated circuits
Languages : en
Pages : 498
Book Description
IEICE Transactions on Electronics
Author:
Publisher:
ISBN:
Category : Electronics
Languages : en
Pages : 936
Book Description
Publisher:
ISBN:
Category : Electronics
Languages : en
Pages : 936
Book Description
Records of the 2002 IEEE International Workshop on Memory Technology, Design and Testing
Author: Bernard Courtois
Publisher: IEEE Computer Society Press
ISBN: 9780769516172
Category : Computers
Languages : en
Pages : 202
Book Description
Annotation MTDT 2002 explores the state-of-the-art in semiconductor memories. Over the last 10 years, the scope of the Workshop has been expanded to cover the fabrication technology and the memory design, test and reliability.
Publisher: IEEE Computer Society Press
ISBN: 9780769516172
Category : Computers
Languages : en
Pages : 202
Book Description
Annotation MTDT 2002 explores the state-of-the-art in semiconductor memories. Over the last 10 years, the scope of the Workshop has been expanded to cover the fabrication technology and the memory design, test and reliability.
Proceedings
Author: IEEE computer society
Publisher:
ISBN: 9780818684944
Category :
Languages : en
Pages : 152
Book Description
Publisher:
ISBN: 9780818684944
Category :
Languages : en
Pages : 152
Book Description
Index to IEEE Publications
Author: Institute of Electrical and Electronics Engineers
Publisher:
ISBN:
Category : Electric engineering
Languages : en
Pages : 848
Book Description
Issues for 1973- cover the entire IEEE technical literature.
Publisher:
ISBN:
Category : Electric engineering
Languages : en
Pages : 848
Book Description
Issues for 1973- cover the entire IEEE technical literature.
Semiconductor Memories
Author: Ashok K. Sharma
Publisher: Wiley-IEEE Press
ISBN: 9780780310001
Category : Technology & Engineering
Languages : en
Pages : 480
Book Description
Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including. * Memory cell structures and fabrication technologies. * Application-specific memories and architectures. * Memory design, fault modeling and test algorithms, limitations, and trade-offs. * Space environment, radiation hardening process and design techniques, and radiation testing. * Memory stacks and multichip modules for gigabyte storage.
Publisher: Wiley-IEEE Press
ISBN: 9780780310001
Category : Technology & Engineering
Languages : en
Pages : 480
Book Description
Semiconductor Memories provides in-depth coverage in the areas of design for testing, fault tolerance, failure modes and mechanisms, and screening and qualification methods including. * Memory cell structures and fabrication technologies. * Application-specific memories and architectures. * Memory design, fault modeling and test algorithms, limitations, and trade-offs. * Space environment, radiation hardening process and design techniques, and radiation testing. * Memory stacks and multichip modules for gigabyte storage.
Testing Semiconductor Memories
Author: A. J. van de Goor
Publisher: John Wiley & Sons
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 542
Book Description
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles, is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory
Publisher: John Wiley & Sons
ISBN:
Category : Technology & Engineering
Languages : en
Pages : 542
Book Description
Comprehensive coverage of memory test problems at chip, array and board level is provided in this book. For each of these test levels a class of fault models is introduced along with tests for these models. The author also presents algorithms of relevant fault models, together with proofs of their correctness. Special attention is given to why a fault model belongs to a particular class and why it is of interest. A software package, suitable for use on IBM PCs and compatibles, is also available which consists of a set of memory test programs and a simulation package demonstrating how the algorithms are executed and the relationship of the algorithm with the memory
Electrical & Electronics Abstracts
Author:
Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 2304
Book Description
Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 2304
Book Description