A 64-channel Mixed-signal Data Acquisition System for a Solid-state High Efficiency Neutron Detector Array PDF Download
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Author:
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ISBN:
Category : Neutron counters
Languages : en
Pages : 150
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Book Description
This thesis presents the design of multiple analog and digital blocks required to implement a desired solid-state data acquisition system for the High Efficiency Neutron Detector Array (HENDA) project under the Spallation Neutron Source (SNS) at Oak Ridge National Laboratory (ORNL). This system encloses and is an extension of prior work described in [1] and [2]. The first prototype chip, named Patara, contained a charge sensitive front-end amplifier [2], and a semi-Gaussian shaper with baseline restore circuitry [1]. Patara III, described in this thesis, involved the addition of the following system components; two comparators, a selectable synchronous/asynchronous digital backend, priority and binary encoders, nine LVDS drivers/receivers, three 8-bit current driven calibration DAC's, two BGR's, and a 99-bit serial shift register with channel test-mode circuitry. The design approach for all major blocks will be discussed along with overall system simulations. In addition, the testing procedure and associated measured results will be summarized illustrating a successful system design. This ASIC was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-[mu]m process available through MOSIS.
Author:
Publisher:
ISBN:
Category : Neutron counters
Languages : en
Pages : 150
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Book Description
This thesis presents the design of multiple analog and digital blocks required to implement a desired solid-state data acquisition system for the High Efficiency Neutron Detector Array (HENDA) project under the Spallation Neutron Source (SNS) at Oak Ridge National Laboratory (ORNL). This system encloses and is an extension of prior work described in [1] and [2]. The first prototype chip, named Patara, contained a charge sensitive front-end amplifier [2], and a semi-Gaussian shaper with baseline restore circuitry [1]. Patara III, described in this thesis, involved the addition of the following system components; two comparators, a selectable synchronous/asynchronous digital backend, priority and binary encoders, nine LVDS drivers/receivers, three 8-bit current driven calibration DAC's, two BGR's, and a 99-bit serial shift register with channel test-mode circuitry. The design approach for all major blocks will be discussed along with overall system simulations. In addition, the testing procedure and associated measured results will be summarized illustrating a successful system design. This ASIC was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-[mu]m process available through MOSIS.
Author: Mahshid Roumi
Publisher:
ISBN: 9781321301267
Category :
Languages : en
Pages : 105
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Book Description
A neutrino is one of the universe's essential ingredients. Neutrinos are very hard to detect because they have no electrical charges and interact little with other particles. Thus, extremely large and sensitive detectors are required to detect neutrinos. The Antarctic Ross Ice shelf ANtenna Neutrino Array (ARIANNA) is a proposed detector for Ultra High Energy (UHE) astrophysical neutrinos. It consists of a surface array of radio receivers and can observe 1 ns radio pulses generated by UHE neutrino interactions with oxygen and hydrogen nuclei in the ice of the Ross Ice Shelf. Each ARIANNA station has four radio frequency antennas, four amplifiers, and a data acquisition system (DAQ). The DAQ of each station has four acquisition channels consisting of four daughter cards and a motherboard. Each daughter card has a custom CMOS digitization and real-time triggering circuitry (ATWD chip), and a field programmable gate array (FPGA) device. The Motherboard has four slots to connect with acquisition cards, another FGPA device for trigger control and data buffering, an embedded CPU with solid-state data storage, and interfaces to an Iridium satellite short burst data transceiver and a long-range wireless communications module. Each acquisition card includes an Advanced Transient Waveform Digitizer (ATWD) chip; a high speed analog sampling, real time pattern matching triggering and digitizing integrated circuit. It has the ability to acquire the incoming waveforms at 2 GHz with over 11-bits of dynamic range. In each station, the acquisition cards receive detected amplified RF signals simultaneously and store them into 128 samples. In addition, the ATWD has the ability to compensate for the fixed pattern noise (FPN) of the sampling and trigger circuitry, which are generated by variations in the gate to drain capacitance in the chip, or variations in the input offsets of the trigger comparators. If left uncorrected, FPN causes variations in trigger thresholds, effectively adding noise in the trigger. Calibration and cancellation of FPN is accomplished by programming per-comparator digital to analog converters to null the FPN at each comparator. After calibration, the RMS trigger noise is reduced by a factor of 3 to 4. The data acquisition system is capable of accepting three types of triggers: external, forced, and thermal. An external trigger acts upon an external electrical input signal much like an oscilloscope's trigger and is used in the laboratory or in the field during experimental studies. A forced trigger is one that is caused by the acquisition system's CPU, and is typically used to force the periodic collection of data that is unbiased by the system's thermal trigger. These "thermal" triggers are the most interesting: they are generated by the signals that the data acquisition system is collecting. Noise - or the rare neutrino events ARIANNA is searching for - will at times cause input signals to exceed trigger thresholds. To allow for low thresholds while keeping trigger rates from being swamped by noise, the thermal trigger system is set up to accept only signal-like events rather than mere noise. This includes requiring bipolar triggers on a per-channel basis over a very brief (~4 ns) time period, plus a requirement that a majority of data acquisition channels (e.g., any 3 out of 4 channels) must all trigger within a brief time window (e.g., 64 ns). These more stringent requirements are expected to capture the vast majority of neutrino events while limiting the rate of "events" due solely to noise. After any triggering event, the sampling of incoming signal is halted, digitized data is read out from the acquisition cards and is stored locally in a solid-state memory card, and then it is transmitted to UC Irvine for further processing over Iridium satellite modem or long-distance wireless communication. This dissertation focuses on the data acquisition system for ARIANNA, most particularly on the design and performance of its trigger system, including FPN calibration and correction and trigger efficiency.
Author: Thomas Michael Oakes
Publisher:
ISBN:
Category : Electronic Dissertations
Languages : en
Pages : 184
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This paper discusses a new neutron detection system that allows local volumetric identification of fast neutron thermalization in the context of forming a solid state Bonner-like neutron spectrometer. The resulting departure and subsequent improvement from the classical Bonner spectrometer is that the entire moderating volume is sampled locally for thermal neutrons. Such volumetric resolution is possible through the layering of weakly perturbing and pixilated high thermal efficiency solid state neutron detectors into a cylindrically symmetric neutron moderator. The overall system exhibits >10% total detection efficiency over the neutron energy range from thermal to 20 MeV and the data can be acquired simultaneously from all detector elements in a single measurement. These measurements can be used to infer information on incident neutron energy spectra and direction, which provides capabilities not available in current systems. The end result is a highly efficient, man-portable device with significantly improved methods for determination of pervading neutron energy spectra and the corresponding dose equivalent.
Author: Helmuth Spieler
Publisher: OUP Oxford
ISBN: 0191523658
Category : Technology & Engineering
Languages : en
Pages : 513
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Book Description
Semiconductor sensors patterned at the micron scale combined with custom-designed integrated circuits have revolutionized semiconductor radiation detector systems. Designs covering many square meters with millions of signal channels are now commonplace in high-energy physics and the technology is finding its way into many other fields, ranging from astrophysics to experiments at synchrotron light sources and medical imaging. This book is the first to present a comprehensive discussion of the many facets of highly integrated semiconductor detector systems, covering sensors, signal processing, transistors and circuits, low-noise electronics, and radiation effects. The diversity of design approaches is illustrated in a chapter describing systems in high-energy physics, astronomy, and astrophysics. Finally a chapter "Why things don't work" discusses common pitfalls. Profusely illustrated, this book provides a unique reference in a key area of modern science.
Author: A. Chesavage
Publisher:
ISBN:
Category : Neutron counters
Languages : en
Pages : 46
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Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 11
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This work reports numerical simulations of a novel three-dimensionally integrated, 1°boron (1°B) and silicon p+, intrinsic, n+ (PIN) diode micropillar array for thermal neutron detection. The inter-digitated device structure has a high probability of interaction between the Si PIN pillars and the charged particles (alpha and 7Li) created from the neutron - 1°B reaction. In this work, the effect of both the 3-D geometry (including pillar diameter, separation and height) and energy loss mechanisms are investigated via simulations to predict the neutron detection efficiency and gamma discrimination of this structure. The simulation results are demonstrated to compare well with the measurement results. This indicates that upon scaling the pillar height, a high efficiency thermal neutron detector is possible.
Author: T. Wang
Publisher:
ISBN:
Category :
Languages : en
Pages : 11
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Book Description
Solid-state thermal neutron detectors are generally fabricated in a planar configuration by coating a layer of neutron-to-alpha converter material onto a semiconductor. The as-created alpha particles in the material are expected to impinge the semiconductor and create electron-hole pairs which provide the electrical signal. These devices are limited in efficiency to a range near (2-5%)/cm{sup 2} due to the conflicting thickness requirements of the converter layer. In this case, the layer is required to be thick enough to capture the incoming neutron flux while at the same time adequately thin to allow the alpha particles to reach the semiconductor. A three dimensional matrix structure has great potential to satisfy these two requirements in one device. Such structures can be realized by using PIN diode pillar elements to extend in the third dimension with the converter material filling the rest of the matrix. Our strategy to fabricate this structure is based on both ''top-down'' and ''bottom-up'' approaches. The ''top down'' approach employs high-density plasma etching techniques, while the ''bottom up'' approach draws on the growth of nanowires by chemical vapor deposition. From our simulations for structures with pillar diameters from 2 {micro}m down to 100 nm, the detector efficiency is expected to increase with a decrease in pillar size. Moreover, in the optimized configuration, the detector efficiency could be higher than 75%/cm{sup 2}. Finally, the road map for the relationship between detector diameter and efficiency will be outlined.
Author:
Publisher:
ISBN:
Category : Electrical engineering
Languages : en
Pages : 2240
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Author:
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ISBN:
Category : Aeronautics
Languages : en
Pages :
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Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :
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The system consists of a data input subsystem, a display subsystem and a spectrometer control subsystem. The data input subsystem consists of a two-dimensional analog-to-digital converter with the analog section remote from the rest of the system. The analog-to-digital converter clock runs at 100 MHz. There can be up to 1024 channels in each dimension for a maximum array size of approx. 1 million words. Arrays of this size may be easily handled by a multiport memory with 6.71 x 107 words of address space. The read/increment/write time for data in this array is 2.5 .mu.sec per event. The display and neutron spectrometer subsystem are also briefly described.
