Triple-threshold Static Power Minimization Technique in High-level Synthesis Using 90nm MTCMOS Technology PDF Download
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Author: Harry I-An Chen
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 0
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Book Description
As CMOS System-on-Chips approach the limits of power dissipation, static power has become dominant in a circuit's total power dissipation. The static power is increasing exponentially as technology nodes shrink and is projected to exceed the dynamic power within the near future. Techniques that use the multi-threshold CMOS (MTCMOS) technology have been developed to reduce static power effectively. In this thesis, a novel triple-threshold static power minimization technique in high-level synthesis has been developed using the 90nm MTCMOS technology. Using static timing analysis, the optimal partitioning of gates with three different threshold voltages is determined via iterative analysis. The proposed triple-threshold technique has been applied to optimize several benchmark circuits, and the results show an average saving in static power close to 90% compared to un-optimized LVT designs. For all designs tested, the triple-threshold technique has produced designs with lower static power compared to a dual-threshold technique.
Author: Harry I-An Chen
Publisher:
ISBN:
Category : Digital integrated circuits
Languages : en
Pages : 0
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Book Description
As CMOS System-on-Chips approach the limits of power dissipation, static power has become dominant in a circuit's total power dissipation. The static power is increasing exponentially as technology nodes shrink and is projected to exceed the dynamic power within the near future. Techniques that use the multi-threshold CMOS (MTCMOS) technology have been developed to reduce static power effectively. In this thesis, a novel triple-threshold static power minimization technique in high-level synthesis has been developed using the 90nm MTCMOS technology. Using static timing analysis, the optimal partitioning of gates with three different threshold voltages is determined via iterative analysis. The proposed triple-threshold technique has been applied to optimize several benchmark circuits, and the results show an average saving in static power close to 90% compared to un-optimized LVT designs. For all designs tested, the triple-threshold technique has produced designs with lower static power compared to a dual-threshold technique.
Author: Nadine Azemard
Publisher: Springer Science & Business Media
ISBN: 354074441X
Category : Computers
Languages : en
Pages : 595
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Book Description
This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Author: Itamar Levi
Publisher: Springer Nature
ISBN: 3030407861
Category : Technology & Engineering
Languages : en
Pages : 191
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Book Description
This book presents Dual Mode Logic (DML), a new design paradigm for digital integrated circuits. DML logic gates can operate in two modes, each optimized for a different metric. Its on-the-fly switching between these operational modes at the gate, block and system levels provide maximal E-D optimization flexibility. Each highly detailed chapter has multiple illustrations showing how the DML paradigm seamlessly implements digital circuits that dissipate less energy while simultaneously improving performance and reducing area without a significant compromise in reliability. All the facets of the DML methodology are covered, starting from basic concepts, through single gate optimization, general module optimization, design trade-offs and new ways DML can be integrated into standard design flows using standard EDA tools. DML logic is compatible with numerous applications but is particularly advantageous for ultra-low power, reliable high performance systems, and advanced scaled technologies Written in language accessible to students and design engineers, each topic is oriented toward immediate application by all those interested in an alternative to CMOS logic. Describes a novel, promising alternative to conventional CMOS logic, known as Dual Mode Logic (DML), with which a single gate can be operated selectively in two modes, each optimized for a different metric (e.g., energy consumption, performance, size); Demonstrates several techniques at the architectural level, which can result in high energy savings and improved system performance; Focuses on the tradeoffs between power, area and speed including optimizations at the transistor and gate level, including alternatives to DML basic cells; Illustrates DML efficiency for a variety of VLSI applications.
Author: Gadi Eisenstein
Publisher: Springer
ISBN: 3319670026
Category : Technology & Engineering
Languages : en
Pages : 299
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Book Description
This books focuses on recent break-throughs in the development of a variety of photonic devices, serving distances ranging from mm to many km, together with their electronic counter-parts, e.g. the drivers for lasers, the amplifiers following the detectors and most important, the relevant advanced VLSI circuits. It explains that as a consequence of the increasing dominance of optical interconnects for high performance workstation clusters and supercomputers their complete design has to be revised. This book thus covers for the first time the whole variety of interdependent subjects contributing to green photonics and electronics, serving communication and energy harvesting. Alternative approaches to generate electric power using organic photovoltaic solar cells, inexpensive and again energy efficient in production are summarized. In 2015, the use of the internet consumed 5-6% of the raw electricity production in developed countries. Power consumption increases rapidly and without some transformational change will use, by the middle of the next decade at the latest, the entire electricity production. This apocalyptic outlook led to a redirection of the focus of data center and HPC developers from just increasing bit rates and capacities to energy efficiency. The high speed interconnects are all based on photonic devices. These must and can be energy efficient but they operate in an electronic environment and therefore have to be considered in a wide scope that also requires low energy electronic devices, sophisticated circuit designs and clever architectures. The development of the next generation of high performance exaFLOP computers suffers from the same problem: Their energy consumption based on present device generations is essentially prohibitive.
Author: Benjamin Chung
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 102
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Book Description
As integrated-circuits (IC) technology advances into the deep-submicron (DSM) regime, more functionality can be combined onto a single chip. One major challenge in designing such a complex device is to keep the power consumption in check while capitalizing on the highest performance that DSM technology can offer. In this thesis we describe a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis technique for designing high-speed low-power SOC applications using 90nm MTCMOS technology. The cell libraries come in fixed threshold - high Vt for good standby power and low Vt for high-speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.
Author: Johan Vounckx
Publisher: Springer Science & Business Media
ISBN: 3540390944
Category : Computers
Languages : en
Pages : 691
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Book Description
This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.
Author: Ajit Pal
Publisher: Springer
ISBN: 8132219376
Category : Technology & Engineering
Languages : en
Pages : 417
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Book Description
The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.
Author: Yuan Taur
Publisher: Cambridge University Press
ISBN: 9781107635715
Category : Technology & Engineering
Languages : en
Pages : 0
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Book Description
Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally renowned authors highlight the intricate interdependencies and subtle trade-offs between various practically important device parameters, and provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model and SiGe-base bipolar devices.
Author: David Flynn
Publisher: Springer Science & Business Media
ISBN: 0387718192
Category : Technology & Engineering
Languages : en
Pages : 303
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Book Description
This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. In addition to providing a theoretical basis for these techniques, the book addresses the practical issues of implementing them in today's designs with today's tools.
Author: Louis Scheffer
Publisher: CRC Press
ISBN: 1420007947
Category : Technology & Engineering
Languages : en
Pages : 544
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Book Description
Presenting a comprehensive overview of the design automation algorithms, tools, and methodologies used to design integrated circuits, the Electronic Design Automation for Integrated Circuits Handbook is available in two volumes. The first volume, EDA for IC System Design, Verification, and Testing, thoroughly examines system-level design, microarchitectural design, logical verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for IC designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. Save on the complete set.
