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Author: Christopher Kaiti Su
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Languages : en
Pages : 0
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This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
Author: Christopher Kaiti Su
Publisher:
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Languages : en
Pages : 0
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Book Description
This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
Author: 魏衍昕
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Languages : en
Pages :
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Author: Manar Ibrahim El-Chammas
Publisher: Stanford University
ISBN:
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Languages : en
Pages : 155
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The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.
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Languages : en
Pages : 0
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Author: Dusan Vlastimir Stepanovic
Publisher:
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Category :
Languages : en
Pages : 228
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Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
Author: 唐梓翔
Publisher:
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Category :
Languages : en
Pages :
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Author: Anu Kalidas Muralidharan Pillai
Publisher: Linköping University Electronic Press
ISBN: 9175190621
Category : Algorithms
Languages : en
Pages : 100
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An analog-to-digital converter (ADC) is a key component in many electronic systems. It is used to convert analog signals to the equivalent digital form. The conversion involves sampling which is the process of converting a continuous-time signal to a sequence of discrete-time samples, and quantization in which each sampled value is represented using a finite number of bits. The sampling rate and the effective resolution (number of bits) are two key ADC performance metrics. Today, ADCs form a major bottleneck in many applications like communication systems since it is difficult to simultaneously achieve high sampling rate and high resolution. Among the various ADC architectures, the time-interleaved analog-to-digital converter (TI-ADC) has emerged as a popular choice for achieving very high sampling rates and resolutions. At the principle level, by interleaving the outputs of M identical channel ADCs, a TI-ADC could achieve the same resolution as that of a channel ADC but with M times higher bandwidth. However, in practice, mismatches between the channel ADCs result in a nonuniformly sampled signal at the output of a TI-ADC which reduces the achievable resolution. Often, in TIADC implementations, digital reconstructors are used to recover the uniform-grid samples from the nonuniformly sampled signal at the output of the TI-ADC. Since such reconstructors operate at the TI-ADC output rate, reducing the number of computations required per corrected output sample helps to reduce the power consumed by the TI-ADC. Also, as the mismatch parameters change occasionally, the reconstructor should support online reconfiguration with minimal or no redesign. Further, it is advantageous to have reconstruction schemes that require fewer coefficient updates during reconfiguration. In this thesis, we focus on reducing the design and implementation complexities of nonrecursive finite-length impulse response (FIR) reconstructors. We propose efficient reconstruction schemes for three classes of nonuniformly sampled signals that can occur at the output of TI-ADCs. Firstly, we consider a class of nonuniformly sampled signals that occur as a result of static timing mismatch errors or due to channel mismatches in TI-ADCs. For this type of nonuniformly sampled signals, we propose three reconstructors which utilize a two-rate approach to derive the corresponding single-rate structure. The two-rate based reconstructors move part of the complexity to a symmetric filter and also simplifies the reconstruction problem. The complexity reduction stems from the fact that half of the impulse response coefficients of the symmetric filter are equal to zero and that, compared to the original reconstruction problem, the simplified problem requires only a simpler reconstructor. Next, we consider the class of nonuniformly sampled signals that occur when a TI-ADC is used for sub-Nyquist cyclic nonuniform sampling (CNUS) of sparse multi-band signals. Sub-Nyquist sampling utilizes the sparsities in the analog signal to sample the signal at a lower rate. However, the reduced sampling rate comes at the cost of additional digital signal processing that is needed to reconstruct the uniform-grid sequence from the sub-Nyquist sampled sequence obtained via CNUS. The existing reconstruction scheme is computationally intensive and time consuming and offsets the gains obtained from the reduced sampling rate. Also, in applications where the band locations of the sparse multi-band signal can change from time to time, the reconstructor should support online reconfigurability. Here, we propose a reconstruction scheme that reduces the computational complexity of the reconstructor and at the same time, simplifies the online reconfigurability of the reconstructor. Finally, we consider a class of nonuniformly sampled signals which occur at the output of TI-ADCs that use some of the input sampling instants for sampling a known calibration signal. The samples corresponding to the calibration signal are used for estimating the channel mismatch parameters. In such TI-ADCs, nonuniform sampling is due to the mismatches between the channel ADCs and due to the missing input samples corresponding to the sampling instants reserved for the calibration signal. We propose three reconstruction schemes for such nonuniformly sampled signals and show using design examples that, compared to a previous solution, the proposed schemes require substantially lower computational complexity.
Author: Daihong Fu
Publisher:
ISBN:
Category :
Languages : en
Pages : 254
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Author: 鄭乙申
Publisher:
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Category :
Languages : en
Pages : 135
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Author: Albert Hsu Ting Chang
Publisher:
ISBN:
Category :
Languages : en
Pages : 199
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As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs). In SAR ADCs, the key linearity and speed limiting factors are capacitor mismatch and incomplete digital-to-analog converter (DAC)/reference voltage settling. In this the- sis, a sub-radix-2 SAR ADC is presented with several new contributions. The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements. The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply. The active die area is 0.083mm2 with full rail-to-rail input swing of 2.4V p-p . A 67.4dB SNDR, 78.1dB SFDR, +1.0/-0.9 LSB12 INL and +0.5/-0.7 LSB12 DNL are achieved at 50MS/s at Nyquist rate. The total power consumption, including the estimated calibration and reference power, is 2.1mW, corresponding to 21.9fJ/conv.- step FoM. This ADC achieves the best FoM of any ADCs with greater than 10b ENOB and 10MS/s sampling rate.
