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Author: Vasilis F. Pavlidis
Publisher: Newnes
ISBN: 0124104843
Category : Technology & Engineering
Languages : en
Pages : 770
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Book Description
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization
Author: Vasilis F. Pavlidis
Publisher: Newnes
ISBN: 0124104843
Category : Technology & Engineering
Languages : en
Pages : 770
Get Book Here
Book Description
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization
Author: Jing Xie
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
The emerging three-dimensional integrated circuits (3D ICs) is one of the most promising solutions for future IC designs. 3D stacking enables much higher memory bandwidth and much lower overhead in multi-power domain design, which provides solutions for chip-multiprocessor design in mitigating the "memory wall" and "dark-silicon" problem. At the same time, 3D technology leads to new opportunities and challenges in the field of circuit and system design techniques, EDA tools and chip testing mechanism. This dissertation presents two killer applications for the modern 3D system and one 3D testing solution. The first contribution of this dissertation is to propose a killer application for TSV based system - the 3D memory stacking. This dissertation presents a 3D memory stacking system that leverages the massive number of TSVs between memory layers to help high-bandwidth checkpointing/restore. To validate the proposed scheme, 2-layer TSV-based SRAM-SRAM 3D-stacked chip is implemented to mimic the high-bandwidth and fast data transfer from one memory layer to another memory layer, so that the in-memory checkpointing/restore scheme can be enabled for the future exascale computing. The capacity of each SRAM layer is 1 Mbit. Each layer contains 64 banks, with each bank contains 256 words and the word length is 64-bit. The final footprint including I/O pad is 2.9mm X 2mm. The SRAM dies were taped out in GlobalFoundries using its 130nm low power process, and the 3D stacking was done by using Tezzaron's TSV technology. The prototyping chip can perform checkpointing/restore at the speed of 4K/cycle with 1Ghz clock.This dissertation also gives an applicable solution for 3D testing. Testing for 3D ICs based on through-silicon-via (TSV) is one of the major challenges for improving the system yield and reducing the overall cost. The lack of pads on most tiers and the mechanical vulnerability of tiers after wafer thinning make it difficult to perform 3D Known-Good-Die (KGD) test with the existing 2D IC probing methods. This dissertation presents a novel and time-efficient 3D testing flow. In this Known-Good-Stack (KGS) flow, a yield-aware TSV defect searching and replacing strategy is introduced. The Build-in-Self-Test (BIST) design with TSV redundancy scheme help improve the system yield for today's imperfect TSV fabrication process. Our study shows that less than 6 redundant TSVs is enough to increase the TSV yield to 98% for a TSV cluster with a size under 16 X 16 with relatively low initial TSV yield. The average TSV cluster testing and self-fixing time is about 3-16 testing cycle depending on the initial TSV yield.The second killer application for 3D system in this dissertation is multi-power domain system design utilizing the monolithic technology. Optimizing energy consumption for electronic systems has been an important design consideration. Among all the techniques, multi-power domain design is a widely used one for low power and high performance applications. In order to perform the data transfer between these different power domains, we needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all require dual power rails, which results in large area and performance overhead. We proposed a scan-able CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. It also has built-in scan feature which makes it testable. Our design separates power rails in each tier, substantially reduced physical design complexity and area penalty. The design is implemented in a 20nm, 28nm and 45nm low power technology. It shows 20%-35% smaller D to Q comparing with normal designs. The proposed design also shows scalability and better energy consumption than precious LCFF design.Finally, we presented a dual power domain deep pipeline circuit architecture for future power-efficient systems. We reduce the power consumption by putting all the combinational logics in a lower power domain, while all the FFs and clock network operate at normal voltage for smaller insertion delay and better clock control. In order to realize these functions and system benefits, we proposed a novel level conversion flip flop omega design, which has 30% insertion delay than the normal flop design and could be easily integrated into today's synthesis flow. This work provides guideline on how to design a dual power domain system with less power under the same system throughput requirement. A system level estimation shows that the 3D dual power supply system could consume about 15% less energy by using our design methodology.
Author: Yuan Xie
Publisher: Springer Science & Business Media
ISBN: 144190784X
Category : Technology & Engineering
Languages : en
Pages : 292
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Book Description
We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).
Author: Rohit Sharma
Publisher: CRC Press
ISBN: 1466589426
Category : Technology & Engineering
Languages : en
Pages : 302
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Book Description
Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text: Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs) Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs) Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications Describes large-scale integration testing and state-of-the-art low-power testing solutions Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal–oxide–semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference that not only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.
Author: Paul D. Franzon
Publisher: John Wiley & Sons
ISBN: 3527338551
Category : Technology & Engineering
Languages : en
Pages : 488
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Book Description
This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.
Author: Guangyu Sun
Publisher: Foundations and Trends(r) in E
ISBN: 9781601984623
Category : Computers
Languages : en
Pages : 166
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Book Description
Presents the background on 3D integration technology, and shows the major benefits offered by 3D integration. EDA design tools and methodologies for 3D ICs are reviewed. The cost of 3D integration is also analyzed.
Author: Banqiu Wu
Publisher: McGraw Hill Professional
ISBN: 0071741968
Category : Technology & Engineering
Languages : en
Pages : 543
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Book Description
The latest advances in three-dimensional integrated circuit stacking technology With a focus on industrial applications, 3D IC Stacking Technology offers comprehensive coverage of design, test, and fabrication processing methods for three-dimensional device integration. Each chapter in this authoritative guide is written by industry experts and details a separate fabrication step. Future industry applications and cutting-edge design potential are also discussed. This is an essential resource for semiconductor engineers and portable device designers. 3D IC Stacking Technology covers: High density through silicon stacking (TSS) technology Practical design ecosystem for heterogeneous 3D IC products Design automation and TCAD tool solutions for through silicon via (TSV)-based 3D IC stack Process integration for TSV manufacturing High-aspect-ratio silicon etch for TSV Dielectric deposition for TSV Barrier and seed deposition Copper electrodeposition for TSV Chemical mechanical polishing for TSV applications Temporary and permanent bonding Assembly and test aspects of TSV technology
Author: Kazuo Kondo
Publisher: Springer
ISBN: 3319186752
Category : Science
Languages : en
Pages : 423
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Book Description
This book starts with background concerning three-dimensional integration - including their low energy consumption and high speed image processing - and then proceeds to how to construct them and which materials to use in particular situations. The book covers numerous applications, including next generation smart phones, driving assistance systems, capsule endoscopes, homing missiles, and many others. The book concludes with recent progress and developments in three dimensional packaging, as well as future prospects.
Author: Aida Todri-Sanial
Publisher: CRC Press
ISBN: 1498710379
Category : Technology & Engineering
Languages : en
Pages : 397
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Book Description
Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.
Author: Sung Kyu Lim
Publisher: Springer Science & Business Media
ISBN: 1441995420
Category : Technology & Engineering
Languages : en
Pages : 573
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Book Description
This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
