The Implementation of a Parallel Automatic Test Pattern Generation System for Sequential Circuits PDF Download
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Author: Donald E. Edenfeld
Publisher:
ISBN:
Category :
Languages : en
Pages : 282
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Book Description
Author: Donald E. Edenfeld
Publisher:
ISBN:
Category :
Languages : en
Pages : 282
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Book Description
Author: Jessica L. Handy
Publisher:
ISBN:
Category :
Languages : en
Pages : 156
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Author: Kee Sup Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 386
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Author: Kyuchull Kim
Publisher:
ISBN:
Category :
Languages : en
Pages : 348
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Author: Byungse So
Publisher:
ISBN:
Category :
Languages : en
Pages : 296
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Author: Soo Y. Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 252
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Book Description
Author: E.H. D'Hollander
Publisher: Elsevier
ISBN: 0080552099
Category : Computers
Languages : en
Pages : 765
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Book Description
This volume gives an overview of the state-of-the-art with respect to the development of all types of parallel computers and their application to a wide range of problem areas. The international conference on parallel computing ParCo97 (Parallel Computing 97) was held in Bonn, Germany from 19 to 22 September 1997. The first conference in this biannual series was held in 1983 in Berlin. Further conferences were held in Leiden (The Netherlands), London (UK), Grenoble (France) and Gent (Belgium). From the outset the aim with the ParCo (Parallel Computing) conferences was to promote the application of parallel computers to solve real life problems. In the case of ParCo97 a new milestone was reached in that more than half of the papers and posters presented were concerned with application aspects. This fact reflects the coming of age of parallel computing. Some 200 papers were submitted to the Program Committee by authors from all over the world. The final programme consisted of four invited papers, 71 contributed scientific/industrial papers and 45 posters. In addition a panel discussion on Parallel Computing and the Evolution of Cyberspace was held. During and after the conference all final contributions were refereed. Only those papers and posters accepted during this final screening process are included in this volume. The practical emphasis of the conference was accentuated by an industrial exhibition where companies demonstrated the newest developments in parallel processing equipment and software. Speakers from participating companies presented papers in industrial sessions in which new developments in parallel computing were reported.
Author: Arndt Bode
Publisher: Springer Science & Business Media
ISBN: 9783540617792
Category : Computers
Languages : en
Pages : 388
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Book Description
This book constitutes the refereed proceedings of the Third European Conference on the Parallel Virtual Machine, EuroPVM '96, the 1996 European PVM users' group meeting, held in Munich, Germany, in October 1996. The parallel virtual machine, PVM, was developed at the University of Tennessee and Oak Ridge National Laboratory in cooperation with Emory University and Carnegie Mellon University to support distributed computing. This volume comprises 51 revised full contributions devoted to PVM. The papers are organized in topical sections on evaluation of PVM; Applications: CFD solvers; tools for PVM; non-numerical applications; extensions to PVM; etc.
Author: Muhammad Nazir Mohammed Khalid
Publisher:
ISBN:
Category : Automatic control
Languages : en
Pages : 186
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Book Description
With a great growing use of electronic products in many aspects of society, it is evident that these products must perform reliably. Their reliability depends on the testing whether or not they have been manufactured properly and behave correctly. To ease testing, digital systems are commonly designed with Built-In Self Test facility. For this reason, development of test pattern for BIST based on combination of Linear Feedback Shift Register (LFSR) and deterministic ATPG (DATPG) approach could provide more solutions, such as reduce testing time, high fault coverage and low area overhead. One of the key challenges in BIST is the design of the Test Pattern Generation (TPG) that promised high fault coverage. The test pattern generation can be generated either manually or automatically. Problems related to ATPG are linked to the controllability and observability of the nodes in circuits. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational circuit. To illustrate that, the DATPG algorithm for digital combinational circuit using VHDL language is designed to generate the test patterns. Altera Max+plus II software is used to simulate the DATPG design to achieve the minimum test patterns for digital combinational circuit. The simulation result will be presented in the form of waveform. The results of DATPG for digital combinational circuit show that the sequence of LFSR has been reduced significantly. In BIST application, the minimum test patterns are applied to the adder/substractor (A/S) known as circuit under test (CUT). A parallel A/S is chosen as a CUT due to the simplicity of the circuit architecture. The A/S is used to verify the proposed DATPG performance. Only one basic cell of the parallel A/S is required to determine the test pattern by considering the data flow from one cell to another. Identical test data can then be applied to both A/S inputs simultaneously. By reducing the number of test pattern, the testing time to market and manufacturing time is expected to reduce leading to reduction in the product cost.
Author: Luciano Lavagno
Publisher: CRC Press
ISBN: 1482254638
Category : Technology & Engineering
Languages : en
Pages : 644
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Book Description
The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.
