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Languages : en
Pages : 0
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Languages : en
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Languages : en
Pages : 17
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This document is a summary of the research activities and results for the seven-month period, 1 April 1988 to 31 October 1988, under the Defense Advanced Research Project Agency (DARPA) Submicron Systems Architecture Project. Previous semiannual technical reports and other technical reports covering parts of the project in detail are listed following these summaries, and can be ordered from the Caltech Computer Science Library. The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes. Our work is focused on VLSI architecture experiments that involve the design, construction, programming, and use of experimental message-passing concurrent computers, and includes related efforts in concurrent computation and VLSI design. Changes in Key Personnel Dr. William C. Athas completed his appointment as a Postdoctoral Research Fellow in Computer Science in August 1988, and has joined the faculty at the University of Texas at Austin as an Assistant Professor of Computer Science. Dr. Stephen Taylor, a new PhD from the Weizmann Institute of Science and the author of a multicomputer implementation of fiat concurrent prolog, joined the project in September 1988 with an appointment at Caltech as an Instructor in Computer Science.
Author: Charles L. Seitz
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Languages : en
Pages : 13
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This project is concerned with the architecture, design, and testing of VLSI Systems. The principal activities in this report period include: The Tree Machine; COPE, The Homogeneous Machine; Computational Arrays; Switch-Level Model for MOS Logic Design; Testing; Local Network and Designer Workstations; Self-timed Systems; Characterization of Deadlock Free Resource Contention; Concurrency Algebra; Language Design and Logic for Program Verification.
Author: California Institute of Technology. Computer Science Department. (CITCS)
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Languages : en
Pages :
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Author:
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Category :
Languages : en
Pages : 17
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The central these of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes. Our work is focused on VLSI architecture experiments that involve the design, construction, programming, and use of experimental multicomputers (message-passing concurrent computers), and includes related efforts in concurrent computation and VLSI design.
Author: Charles L. Seitz
Publisher:
ISBN:
Category : Computer architecture
Languages : en
Pages : 29
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Abstract: "This document is a summary of the research activities and results for the seven-month period, 1 April 1987 to 31 October 1987, under the Defense Advanced Research Project Agency (DARPA) Submicron Systems Architecture Project. Technical reports covering parts of the projects in detail are listed following these summaries, and can be ordered from the Caltech Computer Science Library."
Author: California Institute of Technology
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Category :
Languages : en
Pages : 60
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Author: Charles L. Seitz
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Category : Computer architecture
Languages : en
Pages : 50
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This document reports the research activities and results for the period 16 April 1983 to 15 October 1983 under the Defense Advanced Research Project Agency Submicron Systems Architecture Project. The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes, and includes related efforts in concurrent computation and VLSI design.
Author: Charles L. Seitz
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Category : Integrated circuits
Languages : en
Pages : 54
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Author: Michael Alan Sheets
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Category :
Languages : en
Pages : 308
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In deep-submicron processes a significant portion of the power budget is lost in standby power due to increasing leakage effects. For systems that have long idle times punctuated by bursts of activity, such as PDAs, cell-phones, and wireless sensor networks nodes, this standby power consumption reduces the effectiveness of duty-cycling. This work surveys a number of subthreshold leakage reduction techniques and identifies supply rail gating "MTCMOS" as the most promising. MTCMOS is a dynamic technique that has two distinct modes: an active processing mode and a lower power sleep mode. The smallest area implementations of MTCMOS have the side-effect of losing the state of the system when in sleep mode. This complicates the resumption of the active mode, because traditional designs are intolerent to the loss of state. This work presents a general framework to reduce the state maintenence requirements during sleep mode without losing information required to resume the active mode. The framework is applied to finite state machines and microprocessors, since these are commonly used in system design. Partitioning the system into subsystems with individually controlled supply rails "termed power domains" allows fine-grain control of the power mode for portions of the chip. Each power domain must be dynamically put in the appropriate power mode to ensure correct system operation while minimizing power consumption. This control logic collectively forms the core of a power manager. Most power manager implementation approaches are largely ad-hoc and custom designed for each application. This work presents a structured methodology and architecture for the implementation and control of power domains to form a power managed system. Approaches to the partitioning and implementation of individual power domains are explored. The functional requirements for the power manager
