Selective Epitaxy of Silicon at Low Temperatures

Selective Epitaxy of Silicon at Low Temperatures PDF Author: Jen-Chung Lou
Publisher:
ISBN:
Category :
Languages : en
Pages : 392

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Selective Epitaxy of Silicon at Low Temperatures

Selective Epitaxy of Silicon at Low Temperatures PDF Author: Jen-Chung Lou
Publisher:
ISBN:
Category :
Languages : en
Pages : 392

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Growth and Characterization of Low Temperature Silicon Selective Epitaxy

Growth and Characterization of Low Temperature Silicon Selective Epitaxy PDF Author: Tri-Rung Yew
Publisher:
ISBN:
Category :
Languages : en
Pages : 420

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Low Temperature Selective Silicon Epitaxy at the Nanometer Scale

Low Temperature Selective Silicon Epitaxy at the Nanometer Scale PDF Author: Matthew Mark Sztelle
Publisher:
ISBN: 9780549911173
Category :
Languages : en
Pages : 140

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Book Description
A technique for providing low-temperature, nanometer scale, selective silicon epitaxy using the hydrogen-passivated silicon surface as a lithographic mask has been developed. The STM tip is used to define chemically reactive templates on the monohydride Si(100) surface at temperatures below the monohydride desorption peak, 540 °C. Disilane gas is used to deposit silicon and silicon-hydride species on the exposed clean silicon. For low temperatures (177 °C) or high disilane pressures (1.0x10-8 Torr) the STM tip can be used to remove hydrogen, allowing epitaxy to occur and a fresh silicon surface to be exposed. Repeating this cycle promotes epitaxial growth. At higher temperatures (>177 °C) and lower disilane pressures (≤2.5x10 -9 Torr) short-clean silicon islands form without requiring the STM tip to remove hydrogen in the patterned regions at temperatures below the dihydride desorption peak, 425 °C, thereby adding a processing variable. At sufficient temperatures (310 °C), silicon field-evaporated from the tip may form into an epitaxial film; using this technique, a bilayer of epitaxial growth is demonstrated. The STM tip is used to modify the edges of this structure through the hydrogen removal and selective deposition technique. Also discussed will be the reasonable temperature limits for pattern fidelity.

Low Temperature Selective Silicon Epitaxy by Ultra-high Vacuum Rapid Thermal Chemical Vapor Deposition Using Disilane, Hydrogen and Chlorine

Low Temperature Selective Silicon Epitaxy by Ultra-high Vacuum Rapid Thermal Chemical Vapor Deposition Using Disilane, Hydrogen and Chlorine PDF Author: Katherine Elizabeth Violette
Publisher:
ISBN:
Category :
Languages : en
Pages : 502

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Electrical Testing of Low-temperature Selective Silicon Epitaxy

Electrical Testing of Low-temperature Selective Silicon Epitaxy PDF Author: Daniel Joseph Connelly
Publisher:
ISBN:
Category :
Languages : en
Pages : 350

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Low Temperature Selective Epitaxy of In-situ Doped Silicon and Applications in Nanoscale CMOS

Low Temperature Selective Epitaxy of In-situ Doped Silicon and Applications in Nanoscale CMOS PDF Author: Ibrahim Ban
Publisher:
ISBN:
Category : Epitaxy
Languages : en
Pages : 618

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Silicon Selective Epitaxial Growth by Low Pressure Chemical Vapor Deposition

Silicon Selective Epitaxial Growth by Low Pressure Chemical Vapor Deposition PDF Author: Yangchin Shih
Publisher:
ISBN:
Category :
Languages : en
Pages : 394

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Low Temperature Silicon Selective Epitaxial Growth (SEG) and Phosphorous Doping in a Reduced-pressure Pancake Reactor

Low Temperature Silicon Selective Epitaxial Growth (SEG) and Phosphorous Doping in a Reduced-pressure Pancake Reactor PDF Author: Weichung Wang
Publisher:
ISBN:
Category : Epitaxy
Languages : en
Pages : 96

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Book Description
Since average ideality factors, leakage currents, breakdown voltages, and current gains extracted from 970C̊-40T SEG devices were similar to those of substrate devices, the material quality of the SEG deposited at 970C̊ and 40 torr was indicated to be as good as the bulk silicon."

SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices

SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices PDF Author: John D. Cressler
Publisher: CRC Press
ISBN: 1420066862
Category : Technology & Engineering
Languages : en
Pages : 264

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Book Description
What seems routine today was not always so. The field of Si-based heterostructures rests solidly on the shoulders of materials scientists and crystal growers, those purveyors of the semiconductor “black arts” associated with the deposition of pristine films of nanoscale dimensionality onto enormous Si wafers with near infinite precision. We can now grow near-defect free, nanoscale films of Si and SiGe strained-layer epitaxy compatible with conventional high-volume silicon integrated circuit manufacturing. SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices tells the materials side of the story and details the many advances in the Si-SiGe strained-layer epitaxy for device applications. Drawn from the comprehensive and well-reviewed Silicon Heterostructure Handbook, this volume defines and details the many advances in the Si/SiGe strained-layer epitaxy for device applications. Mining the talents of an international panel of experts, the book covers modern SiGe epitaxial growth techniques, epi defects and dopant diffusion in thin films, stability constraints, and electronic properties of SiGe, strained Si, and Si-C alloys. It includes appendices on topics such as the properties of Si and Ge, the generalized Moll-Ross relations, integral charge-control relations, and sample SiGe HBT compact model parameters.

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond

Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond PDF Author: Guilei Wang
Publisher: Springer Nature
ISBN: 9811500460
Category : Technology & Engineering
Languages : en
Pages : 115

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Book Description
This thesis presents the SiGe source and drain (S/D) technology in the context of advanced CMOS, and addresses both device processing and epitaxy modelling. As the CMOS technology roadmap calls for continuously downscaling traditional transistor structures, controlling the parasitic effects of transistors, e.g. short channel effect, parasitic resistances and capacitances is becoming increasingly difficult. The emergence of these problems sparked a technological revolution, where a transition from planar to three-dimensional (3D) transistor design occurred in the 22nm technology node. The selective epitaxial growth (SEG) method has been used to deposit SiGe as stressor material in S/D regions to induce uniaxial strain in the channel region. The thesis investigates issues of process integration in IC production and concentrates on the key parameters of high-quality SiGe selective epitaxial growth, with a special focus on its pattern dependency behavior and on key integration issues in both 2D and 3D transistor structures, the goal being to improve future applications of SiGe SEG in advanced CMOS.