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Author: Venumadhav Bhagavatula
Publisher:
ISBN:
Category :
Languages : en
Pages : 127
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Book Description
Over the past decade, opportunities for utilizing the broadband spectrum available at millimeter-wave (mm-wave) frequencies has motivated research on both short and long-range, highly-integrated complementary metal oxide semiconductor (CMOS) transceivers. Prototype mm-wave CMOS transceivers have been demonstrated for application in high-speed data transfer (57-64 GHz), wireless back-haul (71-76 GHz), automotive radar (77GHz) and medical imaging (90 GHz) systems. However, in spite of promising results, large scale deployment of mm-wave CMOS transceivers in portable and hand-held electronics is currently hindered by front-end power-consumptions on the order of several watts. Moreover, as a first order approximation, power consumption is directly proportional to system bandwidth. Therefore, as the bandwidth requirements of systems increase, the challenge with on-chip power consumption will become increasingly difficult to solve. In this dissertation, techniques for optimizing the power and area of ultra-wideband millimeter-wave transceivers are described. This work resulted in the fabrication of three mm-wave integrated circuits (IC), all of which were realized in a 6-metal layer 40-nm CMOS process. The first IC is a multi-stage transformer-feedback based 11-to-13 GHz direct-conversion receiver. The device achieves a 16% fractional-bandwidth, a peak power-gain of 27.6dB, and noise-figure of 5.3dB while consuming 28.8mW from a 0.9V supply. Second, a compact 24-54GHz 2-stage bandpass distributed amplifier utilizing mirror-symmetric Norton transformations to reduce inductor component values allowing efficient layout to occupy an active area of 0.15mm2. The device has a 77% fractional-bandwidth, an overall gain of 6.3dB, a minimum in-band IIP3 of 11dBm, while consuming 34mA from a 1V supply. The third, and the IC which includes the most integration among the three, is an ultra-broadband single-element heterodyne receiver intended for use in low-power phased-array systems. The receiver maintains 17GHz of bandwidth from the mm-wave front end, through a high-IF stage, and to the baseband output. The device occupies 1.2mm2 and exploits properties of gain-equalized transformers throughout the signal path to achieve an overall 17GHz bandwidth 20dB gain with a flat in-band response, 7.8dB DSB NF, and a P[subscript-1dB] of -24dBm, while consuming 104mW off a 1.1V supply.
Author: Venumadhav Bhagavatula
Publisher:
ISBN:
Category :
Languages : en
Pages : 127
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Book Description
Over the past decade, opportunities for utilizing the broadband spectrum available at millimeter-wave (mm-wave) frequencies has motivated research on both short and long-range, highly-integrated complementary metal oxide semiconductor (CMOS) transceivers. Prototype mm-wave CMOS transceivers have been demonstrated for application in high-speed data transfer (57-64 GHz), wireless back-haul (71-76 GHz), automotive radar (77GHz) and medical imaging (90 GHz) systems. However, in spite of promising results, large scale deployment of mm-wave CMOS transceivers in portable and hand-held electronics is currently hindered by front-end power-consumptions on the order of several watts. Moreover, as a first order approximation, power consumption is directly proportional to system bandwidth. Therefore, as the bandwidth requirements of systems increase, the challenge with on-chip power consumption will become increasingly difficult to solve. In this dissertation, techniques for optimizing the power and area of ultra-wideband millimeter-wave transceivers are described. This work resulted in the fabrication of three mm-wave integrated circuits (IC), all of which were realized in a 6-metal layer 40-nm CMOS process. The first IC is a multi-stage transformer-feedback based 11-to-13 GHz direct-conversion receiver. The device achieves a 16% fractional-bandwidth, a peak power-gain of 27.6dB, and noise-figure of 5.3dB while consuming 28.8mW from a 0.9V supply. Second, a compact 24-54GHz 2-stage bandpass distributed amplifier utilizing mirror-symmetric Norton transformations to reduce inductor component values allowing efficient layout to occupy an active area of 0.15mm2. The device has a 77% fractional-bandwidth, an overall gain of 6.3dB, a minimum in-band IIP3 of 11dBm, while consuming 34mA from a 1V supply. The third, and the IC which includes the most integration among the three, is an ultra-broadband single-element heterodyne receiver intended for use in low-power phased-array systems. The receiver maintains 17GHz of bandwidth from the mm-wave front end, through a high-IF stage, and to the baseband output. The device occupies 1.2mm2 and exploits properties of gain-equalized transformers throughout the signal path to achieve an overall 17GHz bandwidth 20dB gain with a flat in-band response, 7.8dB DSB NF, and a P[subscript-1dB] of -24dBm, while consuming 104mW off a 1.1V supply.
Author: Domenico Pepe
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology.
Author: Vladimir Kopta
Publisher: CRC Press
ISBN: 1000794490
Category : Technology & Engineering
Languages : en
Pages : 224
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Book Description
Over the past two decades we have witnessed the increasing popularity of the internet of things. The vision of billions of connected objects, able to interact with their environment, is the key driver directing the development of future communication devices. Today, power consumption as well as the cost and size of radios remain some of the key obstacles towards fulfilling this vision. Ultra-Low Power FM-UWB Transceivers for IoT presents the latest developments in the field of low power wireless communication. It promotes the FM-UWB modulation scheme as a candidate for short range communication in different IoT scenarios. The FM-UWB has the potential to provide exactly what is missing today. This spread spectrum technique enables significant reduction in transceiver complexity, making it smaller, cheaper and more energy efficient than most alternative options. The book provides an overview of both circuit-level and architectural techniques used in low power radio design, with a comprehensive study of state-of-the-art examples. It summarizes key theoretical aspects of FM-UWB with a glimpse at potential future research directions. Finally, it gives an insight into a full FM-UWB transceiver design, from system level specifications down to transistor level design, demonstrating the modern power reduction circuit techniques. Ultra-Low Power FM-UWB Transceivers for IoT is a perfect text and reference for engineers working in RF IC design and wireless communication, as well as academic staff and graduate students engaged in low power communication systems research.
Author: Ranjit Gharpurey
Publisher: Springer Science & Business Media
ISBN: 0387692789
Category : Technology & Engineering
Languages : en
Pages : 207
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Book Description
This book is a compilation of chapters on various aspects of Ultra Wideband. The book includes chapters on Ultra Wideband transceiver implementations, pulse-based systems and one on the implementation for the WiMedia/MBOFDM approach. Another chapter discusses the implementation of the physical layer baseband, including the ADC and post-ADC processing required in the UWB system. Future advances such as multiantenna UWB solutions are also discussed.
Author: Ivan Chee-Hong Lai
Publisher: Springer Science & Business Media
ISBN: 1402069995
Category : Technology & Engineering
Languages : en
Pages : 185
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Book Description
Design and Modeling of Millimeter-wave CMOS Circuits for Wireless Transceivers describes in detail some of the interesting developments in CMOS millimetre-wave circuit design. This includes the re-emergence of the slow-wave technique used on passive devices, the license-free 60GHz band circuit blocks and a 76GHz voltage-controlled oscillator suitable for vehicular radar applications. All circuit solutions described are suitable for digital CMOS technology. Digital CMOS technology developments driven by Moore’s law make it an inevitable solution for low cost and high volume products in the marketplace. Explosion of the consumer wireless applications further makes this subject a hot topic of the day. The book begins with a brief history of millimetre-wave research and how the silicon transistor is born. Originally meant for different purposes, the two technologies converged and found its way into advanced chip designs. The second part of the book describes the most important passive devices used in millimetre-wave CMOS circuits. Part three uses these passive devices and builds circuit blocks for the wireless transceiver. The book completes with a comprehensive list of references for further readings. Design and Modeling of Millimeter-wave CMOS Circuits for Wireless Transceivers is useful to show the analogue IC designer the issues involved in making the leap to millimetre-wave circuit designs. The graduate student and researcher can also use it as a starting point to understand the subject or proceed to innovative from the works described herein.
Author: Krzysztof Iniewski
Publisher: CRC Press
ISBN: 0849379970
Category : Technology & Engineering
Languages : en
Pages : 696
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Book Description
Advanced concepts for wireless technologies present a vision of technology that is embedded in our surroundings and practically invisible. From established radio techniques like GSM, 802.11 or Bluetooth to more emerging technologies, such as Ultra Wide Band and smart dust motes, a common denominator for future progress is the underlying integrated circuit technology. Wireless Technologies responds to the explosive growth of standard cellular radios and radically different wireless applications by presenting new architectural and circuit solutions engineers can use to solve modern design problems. This reference addresses state-of-the art CMOS design in the context of emerging wireless applications, including 3G/4G cellular telephony, wireless sensor networks, and wireless medical application. Written by top international experts specializing in both the IC industry and academia, this carefully edited work uncovers new design opportunities in body area networks, medical implants, satellite communications, automobile radar detection, and wearable electronics. The book is divided into three sections: wireless system perspectives, chip architecture and implementation issues, and devices and technologies used to fabricate wireless integrated circuits. Contributors address key issues in the development of future silicon-based systems, such as scale of integration, ultra-low power dissipation, and the integration of heterogeneous circuit design style and processes onto one substrate. Wireless sensor network systems are now being applied in critical applications in commerce, healthcare, and security. This reference, which contains 25 practical and scientifically rigorous articles, provides the knowledge communications engineers need to design innovative methodologies at the circuit and system level.
Author: Ivan Chee-Hong Lai
Publisher: Springer
ISBN: 9781402069987
Category : Technology & Engineering
Languages : en
Pages : 184
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Book Description
Design and Modeling of Millimeter-wave CMOS Circuits for Wireless Transceivers describes in detail some of the interesting developments in CMOS millimetre-wave circuit design. This includes the re-emergence of the slow-wave technique used on passive devices, the license-free 60GHz band circuit blocks and a 76GHz voltage-controlled oscillator suitable for vehicular radar applications. All circuit solutions described are suitable for digital CMOS technology. Digital CMOS technology developments driven by Moore’s law make it an inevitable solution for low cost and high volume products in the marketplace. Explosion of the consumer wireless applications further makes this subject a hot topic of the day. The book begins with a brief history of millimetre-wave research and how the silicon transistor is born. Originally meant for different purposes, the two technologies converged and found its way into advanced chip designs. The second part of the book describes the most important passive devices used in millimetre-wave CMOS circuits. Part three uses these passive devices and builds circuit blocks for the wireless transceiver. The book completes with a comprehensive list of references for further readings. Design and Modeling of Millimeter-wave CMOS Circuits for Wireless Transceivers is useful to show the analogue IC designer the issues involved in making the leap to millimetre-wave circuit designs. The graduate student and researcher can also use it as a starting point to understand the subject or proceed to innovative from the works described herein.
Author: Bagher Afshar
Publisher:
ISBN:
Category :
Languages : en
Pages : 232
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Book Description
Research in the mm-wave band using CMOS and SiGe technologies has gained momentum over the past few years. Millimeter-wave circuits are expected to enter consumer electronics in the near future. 60GHz circuits have the potential to be used in high definition wireless video transmission and high data-rate point-to-point communication. 77GHz has been explored for automotive radar and is expected to become more ubiquitous in coming years. 90GHz has been investigated for imaging and remote sensing applications. Raw silicon transistor performance has improved dramatically in the past decade, which has spurred much of the research. The potential low cost of silicon ICs, especially CMOS, is great motivation to design mm-wave circuits for volume production. This dissertation is divided into two parts. In the first part, the design of a 60GHz CMOS receiver is presented. Design methodologies for robust operation at 60GHz are introduced at device and circuit levels. Key building blocks of a 60GHz receiver are investigated and several design techniques are proposed to increase the performance of the 60GHz circuits. Second part explores the potential of mm-wave design for imaging applications. Performance requirements and challenges of a 90GHz power amplifier for imaging applications are explored. Circuit and system level design details of a pulsed power amplifier are provided and methodologies for enhancing the performance of those designs are introduced. In the end, A prototype of this power amplifier and its integrated version in an ultra wideband pulsed transmitter are presented. This thesis is expected to provide a design framework for achieving predictable and desired performance at mm-wave band.
Author: Kun-Da Chu
Publisher:
ISBN:
Category :
Languages : en
Pages : 144
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Book Description
The demands for higher data rates continue to drive research for consumer products to develop new techniques for low-cost and long battery-life wireless radios. This dissertation explores and implements several single-chip CMOS integrated circuits which aim to enable high data rates for the new spectrum opportunity in future mm-Wave 5G radios as well as to improve the spectrum efficiency for current sub-6GHz communication systems.In the mm-Wave design, a 50-58GHz 2x2 phased-array receiver (RX) for 5G communication and radar systems is described. The RX utilizes a Gm-assisted matching network (MN) to reduce the noise figure (NF) of a conventional passive mixer-first RX by placing an extra gain of ~5dB prior to the down-conversion mixers with minimal additional components. In addition to the Gm-assisted MN, this prototype phased-array RX integrates a proposed Gm-assisted MN, mixer-first RX with translational feedback, Cartesian phase shifters as a baseband beamformer, poly-phase filters, and LO generation in TSMC 28nm CMOS, occupying a total area of 0.53mm2. This RX achieves a NF of 7dB, gain of 26dB, input P1-dB of -20dBm with an 8-GHz 3-dB BW and a S11 lower than -10dB over 22-GHz BW. Second, a novel highly-digital 2x2 phased-array receiver implemented in TSMC 28-nm CMOS with several techniques, including a feedforward noise-suppressing front-end, reconfigurable 0-3 SMASH CT-delta-sigma ADC, and digital beamformer. This proposed receiver enables the development of digital multi-beam phased-array with improved front-end NF, reduced silicon area, and low power consumption for future wireless systems. Third, a dual-mode V-band power amplifier (PA) that utilizes a reconfigurable 2/4-way power combiner is introduced to enable two discrete modes of operation and enhance the efficiency at power back-off. The power combiner employs two techniques to further improve the PA efficiency at power back-off: 1) usage of transformers with non-uniform turns ratios to reduce the difference in impedance presented to the PA cores between the two modes and 2) utilize a proposed switching scheme to eliminate the leakage inductance associated with the disabled path in back-off power mode. The 2-stage PA achieves a peak gain of 21.4dB with a fractional BW (fBW) of 22.6% (51-64GHz). At 65GHz, the PA has a Psat of +17.9dBm with an OP1dB of +13.5dBm and a peak PAE of 26.5% in full-power mode. In back-off power mode, the measured Psat, OP1dB, and peak PAE are +13.8dBm, +9.6dBm, and 18.4%, respectively. The PAE is enhanced by 6% points at a 4.5-dB back-off. The PA is capable of amplifying a 6-Gb/s 16-QAM modulated signal with an EVMrms of -20.7dB at an average Pout/PAE of +13dBm/13.6%, respectively. This PA was implemented in 16-nm FinFET, occupies a core area of 0.107mm2, and operates under a 0.95-V supply. Lastly, to improve spectrum usage of the current sub-6GHz systems, a triple-path transmitter (TX) self-interference cancellation (SIC) transceiver for full-duplex (FD) systems which achieves greater than 73dB of SIC is reported. An integrated electrical balance duplexer (EBD) is employed and works in concert with two pre- and post-LNA RF feedforward cancelers implemented as analog finite impulse response (FIR) filters to form a combined three-path cancellation architecture that achieves a deep on-chip TX SIC over a very wide bandwidth (BW). The on-chip self-interference cancellation of 72.8/70.1/65.2dB was measured by comparing integrated channel power difference at the receiver (RX) baseband (BB) output while applying orthogonal frequency-division multiplexing (OFDM) multi-carrier 64-QAM Wi-Fi packages at the transmitter input with a 20/40/80-MHz bandwidth, respectively. The receiver noise figure (NF) degradation due to the TX SI leakage improves from 8dB to 1.6dB after turning on both RF cancelers. TX SI leakage reciprocal mixing with the RX LO phase noise (PN) was also significantly reduced by 11dB up to 1-MHz offset frequency measured at RX BB output. This work integrates the whole transceiver signal path from the analog baseband to RF. The FD prototype chip is fabricated in TSMC 40nm CMOS process with a die size of 4mm2 that consumes 106mW (excluding PA). An Altera Cyclone III FPGA with ADC/DAC daughter board is used to emulate the digital baseband (BB) and executes a nearest neighbor search (NNS) algorithm to close the filter adaptation loop. The RX operates from 1.6GHz to 1.9GHz with a total noise figure of 8.09dB and an IIP3 of -17dBm while operating at the highest gain of 42dB. The TX has an output P-1dB/Psat of 10.6dBm/12.5dBm measured at the antenna port, respectively. This chip also integrates an integer-N synthesizer with a measured locking range from 3.52GHz to 4.28GHz. The synthesizer consumes 10.4mW with a phase noise performance of -117dBc/Hz measured at 1-MHz frequency offset. These four prototypes demonstrate various techniques to reduce power and area for future wireless systems, including the applications in mm-Wave front-ends for new spectrum opportunities with increased data rates as well as improved spectral efficient full-duplex radios for existing sub-6GHz bands.
Author:
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
Abstract: The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers.
