Author: Alok Barua
Publisher:
ISBN: 9780750317313
Category : Analog-to-digital converters
Languages : en
Pages : 0
Book Description
Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering.
Pipelined Analog to Digital Converter and Fault Diagnosis
Author: Alok Barua
Publisher:
ISBN: 9780750317313
Category : Analog-to-digital converters
Languages : en
Pages : 0
Book Description
Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering.
Publisher:
ISBN: 9780750317313
Category : Analog-to-digital converters
Languages : en
Pages : 0
Book Description
Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering.
Pipelined Analog to Digital Converter and Fault Diagnosis
Author: Alok Barua
Publisher:
ISBN: 9780750317689
Category :
Languages : en
Pages : 184
Book Description
Pipelined analog to digital converters (ADCs) have become the architecture of choice for high-speed and moderate- to high-resolution devices. Subsequently, different techniques of fault diagnosis by the built-in self-test (BIST) system have been developed. An ideal reference for graduate students and researchers within electrical, electronics and computer engineering, this book provides a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed.
Publisher:
ISBN: 9780750317689
Category :
Languages : en
Pages : 184
Book Description
Pipelined analog to digital converters (ADCs) have become the architecture of choice for high-speed and moderate- to high-resolution devices. Subsequently, different techniques of fault diagnosis by the built-in self-test (BIST) system have been developed. An ideal reference for graduate students and researchers within electrical, electronics and computer engineering, this book provides a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed.
Fault Diagnosis and Residue Stage Redesign for an 8-bit 20 MSamples/S, Pipelined Analog-to-digital Converter in 0.5[mu]m CMOS
Author: Amol Deshmane
Publisher:
ISBN:
Category :
Languages : en
Pages : 148
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 148
Book Description
Fault Diagnosis and Comparator Redesign for an 8-bit 20ms/s Calibrated Pipelined Analog-to-digital Converter in 0.5um CMOS
Author: Nicholas Thomas Martin
Publisher:
ISBN:
Category :
Languages : en
Pages : 88
Book Description
This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5 (micro)m CMOS process technology. This integrated circuit was designed using a 1.5 bit/stage pipelined architecture and uses seven stages, which forms the most critical part of the chip referred to as the 'pipeline core'. From the information received from the advisors of the previous team, the comparator included an adjustable reset time design-for-test (DFT) feature, but test results indicated minimal adjust range of the reset time.My part of this project was focused on the diagnosis and redesign of the comparator located within the Sub-ADC of the pipeline core.
Publisher:
ISBN:
Category :
Languages : en
Pages : 88
Book Description
This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5 (micro)m CMOS process technology. This integrated circuit was designed using a 1.5 bit/stage pipelined architecture and uses seven stages, which forms the most critical part of the chip referred to as the 'pipeline core'. From the information received from the advisors of the previous team, the comparator included an adjustable reset time design-for-test (DFT) feature, but test results indicated minimal adjust range of the reset time.My part of this project was focused on the diagnosis and redesign of the comparator located within the Sub-ADC of the pipeline core.
Fault Diagnosis and Sub-ADC Redesign for an 8-bit 20 Msamples/s Pipelined Analog-to-digitatl Converter in 0.5-um CMOS Process
Author: Deepan Sheth
Publisher:
ISBN:
Category :
Languages : en
Pages : 78
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 78
Book Description
Pipelined Analog-to-digital Conversion Using Class-AB Amplifiers
Author: Kyung Ryun Kim
Publisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 128
Book Description
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Publisher: Stanford University
ISBN:
Category :
Languages : en
Pages : 128
Book Description
In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.
Noise, Speed, and Power Tradeoffs in Pipelined Analog to Digital Converters
Author: David William Cline
Publisher:
ISBN:
Category :
Languages : en
Pages : 786
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 786
Book Description
Digitally Enhanced High Resolution Pipelined Analog-to-digital Conversion
Author: Eric John Siragusa
Publisher:
ISBN:
Category :
Languages : en
Pages : 132
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 132
Book Description
Design of a Pipelined Analog-to-digital Converter
Author: Chan Oe Lee
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Publisher:
ISBN:
Category :
Languages : en
Pages : 168
Book Description
Analog Background Calibration of Parallel Pipelined Analog-to-digital Converters
Author: Kenneth Colin Dyer
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 300
Book Description
Publisher:
ISBN:
Category : Analog-to-digital converters
Languages : en
Pages : 300
Book Description