Next Generation Wireless Receiver Architecture Design in Deep-Sub-Micron CMOS Technology PDF Download
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Author: Chaoying (Charles) Wu
Publisher:
ISBN:
Category :
Languages : en
Pages : 184
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Book Description
Current advances in wireless receiver technologies are primarily driven by the need for cost reduction through (1) integration of a radio, an ADC and a digital processor on a single CMOS die, and (2) the design of low-power multi-standard capable receivers. However, due to the spectrum scarcity, future wireless standards, such as LTE, present a whole new set of challenges for radio system design. For example, LTE's highly fragmented spectrum requires multiple chipsets for support. Due to this cost overhead, there is no global LTE-enabled device available in the market now. Moreover, while carrier aggregation (CA) added to LTE brings unparalleled data rate improvement, it seriously complicates the RF frontend design. Modern commercial LTE solutions include multiple chipsets to support various scenarios of CA, which is not cost effective. This work focuses on novel receiver architectures that address the design challenges associated with LTE-Advance from two perspectives: (1) a receiver that is capable of wide-frequency range of operation to cover all the LTE bands and (2) a single highly linear RF frontend to support non-contiguous-in-band CA. A novel sigma-delta-based direct-RF-to-digital receiver architecture is introduced in this work as an example of a complete integrated RF-to-digital frontend design capable to cover all the LTE bands. The design is implemented in 65 nm CMOS technology and the SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB over the 400 MHz to 4 GHz frequency range. In a different example, we propose a passive-mixer-first receiver system to provide CA support in a cost-effective and power-efficient manner. Mixer-first receiver's superb linearity performance enables the possibility of a single receiver processing the entire LTE RX band, while most of the signal conditioning can be pushed into DSP to enjoy the benefit of process scaling. This design has been demonstrated in a 28 nm bulk CMOS technology, and the overall system achieves 3 dB NF, 15 dBm IIP3 and 35 dB gain with 60 mW of power.
Author: Chaoying (Charles) Wu
Publisher:
ISBN:
Category :
Languages : en
Pages : 184
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Book Description
Current advances in wireless receiver technologies are primarily driven by the need for cost reduction through (1) integration of a radio, an ADC and a digital processor on a single CMOS die, and (2) the design of low-power multi-standard capable receivers. However, due to the spectrum scarcity, future wireless standards, such as LTE, present a whole new set of challenges for radio system design. For example, LTE's highly fragmented spectrum requires multiple chipsets for support. Due to this cost overhead, there is no global LTE-enabled device available in the market now. Moreover, while carrier aggregation (CA) added to LTE brings unparalleled data rate improvement, it seriously complicates the RF frontend design. Modern commercial LTE solutions include multiple chipsets to support various scenarios of CA, which is not cost effective. This work focuses on novel receiver architectures that address the design challenges associated with LTE-Advance from two perspectives: (1) a receiver that is capable of wide-frequency range of operation to cover all the LTE bands and (2) a single highly linear RF frontend to support non-contiguous-in-band CA. A novel sigma-delta-based direct-RF-to-digital receiver architecture is introduced in this work as an example of a complete integrated RF-to-digital frontend design capable to cover all the LTE bands. The design is implemented in 65 nm CMOS technology and the SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB over the 400 MHz to 4 GHz frequency range. In a different example, we propose a passive-mixer-first receiver system to provide CA support in a cost-effective and power-efficient manner. Mixer-first receiver's superb linearity performance enables the possibility of a single receiver processing the entire LTE RX band, while most of the signal conditioning can be pushed into DSP to enjoy the benefit of process scaling. This design has been demonstrated in a 28 nm bulk CMOS technology, and the overall system achieves 3 dB NF, 15 dBm IIP3 and 35 dB gain with 60 mW of power.
Author: Johan Janssens
Publisher: Springer Science & Business Media
ISBN: 0792376374
Category : Computers
Languages : en
Pages : 267
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Book Description
CMOS Cellular Receiver Front-Ends: From Specification to Realization deals with the design of the receive path of a highly-integrated CMOS cellular transceiver for the GSM-1800 cellular system. The complete design trajectory is covered, starting from the documents describing the standard down to the systematic development of CMOS receiver ICs that comply to the standard. The design of CMOS receivers is tackled at all abstraction levels: from architecture level, via circuit level, down to the device level, and the other way around. Different receiver architectures are compared with respect to integratability, achievable performance and required building block specifications. The requirements of the GSM-1800 standard are mapped onto a set of measurable specifications for a highly-integrated low-IF receiver and distributed among the different building blocks. Several circuit topologies are presented that realize the main functions of the receive path. The dynamics of the elementary specifications of these circuits are explained in terms of the operating point of the involved devices. Wherever possible, this is done using analytical expressions. Based on these insights, detailed sizing procedures are developed to systematically size these RF circuits for a set of specifications. The feasibility of meeting the requirements of today's high-end cellular standards is demonstrated in a mainstream submicron CMOS technology by the development of two highly-integrated GSM-1800 receivers. The theoretical core of the book discusses the fundamental and more advanced aspects of RF CMOS design. It focuses specifically on all aspects of the design of high-performance CMOS low-noise amplifiers. Attempts are made to reconcile the analog designer's and the RF designer's point of view on how to look at submicron CMOS transistors. Special attention is given to the fallacies and pitfalls of input matching in a CMOS context. A methodology for the systematic design of CMOS low-noise amplifiers is presented which is based on a bank of analytical equations for all important LNA specifications. The method is validated by the design of a low power, extremely low noise CMOS GPS LNA.
Author: Kostas Doris
Publisher: Elsevier Inc. Chapters
ISBN: 0128064560
Category : Technology & Engineering
Languages : en
Pages : 41
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Book Description
This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance. The impact of interleaving mismatches on representative broadband and multi-carrier narrowband signals is also discussed. Next, two examples are given demonstrating how interleaving with many ADCs can be transformed from a weakness to a strength. The first example concerns low spurious performance enabled by redundant SAR converters and randomization of their operation. The second example presents spectral sensing techniques.
Author: Domenico Pepe
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology.
Author: Sung Min Park
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
Author: Imed Ben Dhaou
Publisher:
ISBN:
Category :
Languages : en
Pages : 364
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Book Description
![A Study in Low-power Wireless Transceiver Architectures in Submicron CMOS Technology [microform] PDF](https://books.google.com/books/content/images/frontcover/O9B9AAAACAAJ?fife=w80-h100)
Author: Hesham Nabil Mohamed Ahmed
Publisher: Library and Archives Canada = Bibliothèque et Archives Canada
ISBN: 9780612978096
Category : Low voltage integrated circuits
Languages : en
Pages : 300
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Book Description
Author: Jan Crols
Publisher: Springer Science & Business Media
ISBN: 1475747845
Category : Technology & Engineering
Languages : en
Pages : 249
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Book Description
The world of wireless communications is changing very rapidly since a few years. The introduction of digital data communication in combination with digital signal process ing has created the foundation for the development of many new wireless applications. High-quality digital wireless networks for voice communication with global and local coverage, like the GSM and DECT system, are only faint and early examples of the wide variety of wireless applications that will become available in the remainder of this decade. The new evolutions in wireless communications set new requirements for the trans ceivers (transmitter-receivers). Higher operating frequencies, a lower power consump tion and a very high degree of integration, are new specifications which ask for design approaches quite different from the classical RF design techniques. The integrata bility and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. This is however completely different for the analog transceiver front-end, the part which performs the interfacing between the antenna and the digital signal processing. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Chapter 2 gives a detailed study of the level of integration in current transceiver realization and analyzes their limitations. In chapter 3 of this book the complex signal technique for the analysis and synthesis of multi-path receiver and transmitter topologies is introduced.
Author: Joy Laskar
Publisher: John Wiley & Sons
ISBN: 047147486X
Category : Technology & Engineering
Languages : en
Pages : 240
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Book Description
Architectures BABAK MATINPOUR and JOY LASKAR * Describes the actual implementation of receiver architectures from the initial design to an IC-based product * Presents many tricks-of-the-trade not usually covered in textbooks * Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis * Discusses architectures that are employed in modern broadband wireless systems
Author: Ville Saari
Publisher: Springer Science & Business Media
ISBN: 1461433657
Category : Technology & Engineering
Languages : en
Pages : 207
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Book Description
This book presents a new filter design approach and concentrates on the circuit techniques that can be utilized when designing continuous-time low-pass filters in modern ultra-deep-submicron CMOS technologies for integrated wideband radio receivers. Coverage includes system-level issues related to the design and implementation of a complete single-chip radio receiver and related to the design and implementation of a filter circuit as a part of a complete single-chip radio receiver. Presents a new filter design approach, emphasizing low-voltage circuit solutions that can be implemented in modern, ultra-deep-submicron CMOS technologies;Includes filter circuit implementations designed as a part of a single-chip radio receiver in modern 1.2V 0.13um and 65nm CMOS;Describes design and implementation of a continuous-time low-pass filter for a multicarrier WCDMA base-station;Emphasizes system-level considerations throughout.
