Author: Benjamin Smith
Publisher:
ISBN: 9780494273289
Category :
Languages : en
Pages : 156
Get Book Here
Book Description
This thesis presents new methods to design low-density parity-check (LDPC) codes with reduced decoding complexity. An accurate measure of iterative decoding complexity is introduced. In conjunction with extrinsic information transfer (EXIT) chart analysis, an efficient optimization program is developed, for which the complexity measure is the objective function, and its utility is demonstrated by designing LDPC codes with reduced decoding complexity. For long block lengths, codes designed by these methods match the performance of threshold-optimized codes, but reduce the decoding complexity by approximately one-third. The performance of LDPC codes is investigated when the decoder is constrained to perform a sub-optimal decoding algorithm. Due to their practical relevance, the focus is on the design of LDPC codes for quantized min-sum decoders. For such a decoder, codes designed for the sum-product algorithm are sub-optimal, and an alternative design strategy is proposed, resulting in gains of more than 0.5 dB.
Author: Vikram Arkalgud Chandrasetty
Publisher: Academic Press
ISBN: 0128112565
Category : Technology & Engineering
Languages : en
Pages : 192
Get Book Here
Book Description
This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach – from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.The reader will learn: Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation How to reduce computational complexity and power consumption using computer aided design techniques All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs Provides extensive treatment of LDPC decoding algorithms and hardware implementations Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis
Author: Chen Jinghu
Publisher:
ISBN:
Category : Decoders (Electronics)
Languages : en
Pages : 234
Get Book Here
Book Description
Author: Mayank Ardeshana
Publisher: LAP Lambert Academic Publishing
ISBN: 9783845420417
Category :
Languages : en
Pages : 72
Get Book Here
Book Description
Channel coding provides the means of patterning signals so as to reduce their energy or bandwidth consumption for a given error performance. LDPC codes have been shown to have good error correcting performance which enables efficient and reliable communication. LDPC codes have linear decoding complexity but performance approaching close to shannon capacity with iterative probabilistic decoding algorithm. In this dissertation, the performance of different error correcting code such as convolution, Reed Solomon(RS), hamming, block code are evaluated based on different parameters like code rate, bit error rate (BER), Eb/No, complexity, coding gain and compare with LDPC code. In general, message passing algorithm and the sum-product algorithm are used to decode the message. We showed that logarithmic sum-product algorithm with long block length code reduces multiplication to addition by introducing logarithmic likelihood ratio so that it achieves the highest BER performance among all the decoding algorithms. The astonishing performance combined with proposed modified MS decoding algorithm make these codes very attractive for the next generations digital broadcasting system (ABS - S).
Author: Kevin Cushon
Publisher:
ISBN:
Category :
Languages : en
Pages :
Get Book Here
Book Description
"Low-density parity-check (LDPC) codes are a type of error correcting code that are frequently used in high-performance communications systems, due to their ability to approach the theoretical limits of error correction. However, their iterative soft-decision decoding algorithms suffer from high computational complexity, energy consumption, and auxiliary circuit implementation difficulties. It is of particular interest to develop energy-efficient LDPC decoders in order to decrease cost of operation, increase battery life in portable devices, lessen environmental impact, and increase the range of applications for these powerful codes.In this dissertation, we propose four new LDPC decoder designs with the primary goal of improving energy efficiency over previous designs. First, we present a bidirectional interleaver based on transmission gates, which reduces wiring complexity and associated parasitic energy losses. Second, we present an iterative decoder design based on pulse-width modulated min-sum (PWM-MS). We demonstrate that the pulse width message format reduces switching activity, computational complexity, and energy consumption compared to other recent LDPC decoder designs. Third, wepresent decoders based on differential binary (DB) algorithms. We also propose an improved differential binary (IDB) decoding algorithm, which greatly increases throughput and reduces energy consumption compared to recent decoders ofsimilar error correction capability. Finally, we present decoders based on gear-shift algorithms, which use multiple decoding rules to minimize energy consumption. We propose gear-shift pulse-width (GSP) and IDB with GSP (IGSP) algorithms, and demonstrate that they achieve superior energy efficiency without compromising error correction performance." --
Author: Abhiram Prabhakar
Publisher:
ISBN:
Category :
Languages : en
Pages : 136
Get Book Here
Book Description
Author: Fang Cai
Publisher:
ISBN:
Category :
Languages : en
Pages : 149
Get Book Here
Book Description
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this thesis, three decoding algorithms and corresponding VLSI architectures are proposed for NB-LDPC codes to lower the computational complexity and memory requirement. The first design is based on the proposed relaxed Min-max decoding algorithm. A novel relaxed check node processing scheme is proposed for the Min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p̂) can be uniquely represented by a linear combination of $p$ independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25̂) can achieve 52% higher efficiency in terms of throughput-over-area ratio. The second design is based on a proposed enhanced iterative hard reliability-based majority-logic decoding. The recently developed iterative hard reliability-based majority-logic NB-LDPC decoding has better performance-complexity tradeoffs than previous algorithms. Novel schemes are proposed for the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E- )IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Many existing NB-LDPC code construction methods lead to quasi-cyclic or cyclic codes. Both types of codes are considered in our design. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous designs based on the Min-max decoding algorithm, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss. The third design is based on a proposed check node decoding scheme using power representation of finite field elements. Novel schemes are proposed for the Min-max check node processing by making use of the cyclical-shift property of the power representation of finite field elements. Compared to previous designs based on the Min-max algorithm with forward-backward scheme, the proposed check node units (CNUs) do not need the complex switching network. Moreover, the multiplications of the parity check matrix entries are efficiently incorporated. For a Min-max NB-LDPC decoder over GF(32), the proposed scheme reduces the CNU area by at least 32%, and leads to higher clock frequency.
Author: Jeff Castura
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
Get Book Here
Book Description
Reduced complexity decoding algorithms for Low Density Parity Check codes are presented. The performance of these algorithms is optimized using the concept of density evolution and they are shown to perform well in practical decoding situations. The codes are examined from a performance vs. complexity point of view. It is shown that there is an optimal complexity for practical decoders beyond which performance will suffer. The idea of practical decoding is used to develop the sum-transform-sum algorithm, which is very well suited for a fixed-point hardware implementation. The performance of this algorithm approaches that of the sum-product algorithm, but is much less complex.
Author: Martin Tomlinson
Publisher: Springer
ISBN: 3319511033
Category : Technology & Engineering
Languages : en
Pages : 527
Get Book Here
Book Description
This book discusses both the theory and practical applications of self-correcting data, commonly known as error-correcting codes. The applications included demonstrate the importance of these codes in a wide range of everyday technologies, from smartphones to secure communications and transactions. Written in a readily understandable style, the book presents the authors’ twenty-five years of research organized into five parts: Part I is concerned with the theoretical performance attainable by using error correcting codes to achieve communications efficiency in digital communications systems. Part II explores the construction of error-correcting codes and explains the different families of codes and how they are designed. Techniques are described for producing the very best codes. Part III addresses the analysis of low-density parity-check (LDPC) codes, primarily to calculate their stopping sets and low-weight codeword spectrum which determines the performance of th ese codes. Part IV deals with decoders designed to realize optimum performance. Part V describes applications which include combined error correction and detection, public key cryptography using Goppa codes, correcting errors in passwords and watermarking. This book is a valuable resource for anyone interested in error-correcting codes and their applications, ranging from non-experts to professionals at the forefront of research in their field. This book is open access under a CC BY 4.0 license.
Author: William Ryan
Publisher: Cambridge University Press
ISBN: 1139483013
Category : Technology & Engineering
Languages : en
Pages : 709
Get Book Here
Book Description
Channel coding lies at the heart of digital communication and data storage, and this detailed introduction describes the core theory as well as decoding algorithms, implementation details, and performance analyses. In this book, Professors Ryan and Lin provide clear information on modern channel codes, including turbo and low-density parity-check (LDPC) codes. They also present detailed coverage of BCH codes, Reed-Solomon codes, convolutional codes, finite geometry codes, and product codes, providing a one-stop resource for both classical and modern coding techniques. Assuming no prior knowledge in the field of channel coding, the opening chapters begin with basic theory to introduce newcomers to the subject. Later chapters then extend to advanced topics such as code ensemble performance analyses and algebraic code design. 250 varied and stimulating end-of-chapter problems are also included to test and enhance learning, making this an essential resource for students and practitioners alike.
