High-frequency Synthesis Using Phase-locked Loops for Wide Tuning-range Applications and Sub-1 V Operation in Deep Submicron CMOS Processes PDF Download
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Author: Omar Abdel Fattah
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Frequency synthesizers based on phase-locked loop (PLL) are ubiquitous components in RF communication systems. Frequency synthesizer PLLs must comply with the stringent requirements of RF systems such as noise, linearity, locking time, stability, and power consumption. The continuous shrinkage of the technology dimensions and power supply values exacerbated the situation and made the design more daunting especially at high frequencies. Integrability and long-life batteries have become extremely important targets in modern life. The ability to incorporate multiple standards in one device has recently stimulated a great deal of interest and brought to existence applications such as software-defined radio (SDR) and cognitive radio (CR). Such applications require very wide tuning range frequency synthesizers to cover multiple standards. The ability to cover this wide range with a single frequency synthesizer PLL is very desirable in terms of cost, area, and power. In this thesis, we tackle high frequency synthesis in light of the challenges imposed by modern CMOS technologies. More specifically, we tackle two design challenges. The first challenge is the need for wide tuning-range frequency synthesizer PLLs; and the second challenge is the need for analog circuits, including frequency synthesizer PLLs, that can operate from supply voltages below 0.6 V as predicted by semiconductor roadmaps for the next decade. In response to these technology demands, we provide three different IC implementations with measurement results to verify the theoretical findings. We demonstrate two frequency synthesizer PLLs in 65 nm CMOS technology. The first PLL focuses on wide tuning-range for applications such as SDR and CR, while operating from a supply voltage as low as 1.2 V. A continuous frequency range from 156.25 MHz to 10 GHz is achieved using a single frequency synthesizer PLL. The second PLL focuses on sub-1 V operation to generate a low-noise output. This PLL operates from a 0.55 V power supply and consumes 3 mW of power. The designed PLLs show comparable performance with the state-of-the-art PLLs in the literature in CMOS and other technologies. Furthermore, a third IC implementation of an ultra-low-voltage operational-transconductance-amplifier (OTA) is presented. The OTA combines different low-voltage techniques along with a novel biasing technique that allows operation from a supply voltage as low as 0.35 V. The ultra-low-voltage OTA can be used as a building block for the design of other biasing circuitry at low voltage such as bandgap references and voltage regulators." --
Author: Omar Abdel Fattah
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"Frequency synthesizers based on phase-locked loop (PLL) are ubiquitous components in RF communication systems. Frequency synthesizer PLLs must comply with the stringent requirements of RF systems such as noise, linearity, locking time, stability, and power consumption. The continuous shrinkage of the technology dimensions and power supply values exacerbated the situation and made the design more daunting especially at high frequencies. Integrability and long-life batteries have become extremely important targets in modern life. The ability to incorporate multiple standards in one device has recently stimulated a great deal of interest and brought to existence applications such as software-defined radio (SDR) and cognitive radio (CR). Such applications require very wide tuning range frequency synthesizers to cover multiple standards. The ability to cover this wide range with a single frequency synthesizer PLL is very desirable in terms of cost, area, and power. In this thesis, we tackle high frequency synthesis in light of the challenges imposed by modern CMOS technologies. More specifically, we tackle two design challenges. The first challenge is the need for wide tuning-range frequency synthesizer PLLs; and the second challenge is the need for analog circuits, including frequency synthesizer PLLs, that can operate from supply voltages below 0.6 V as predicted by semiconductor roadmaps for the next decade. In response to these technology demands, we provide three different IC implementations with measurement results to verify the theoretical findings. We demonstrate two frequency synthesizer PLLs in 65 nm CMOS technology. The first PLL focuses on wide tuning-range for applications such as SDR and CR, while operating from a supply voltage as low as 1.2 V. A continuous frequency range from 156.25 MHz to 10 GHz is achieved using a single frequency synthesizer PLL. The second PLL focuses on sub-1 V operation to generate a low-noise output. This PLL operates from a 0.55 V power supply and consumes 3 mW of power. The designed PLLs show comparable performance with the state-of-the-art PLLs in the literature in CMOS and other technologies. Furthermore, a third IC implementation of an ultra-low-voltage operational-transconductance-amplifier (OTA) is presented. The OTA combines different low-voltage techniques along with a novel biasing technique that allows operation from a supply voltage as low as 0.35 V. The ultra-low-voltage OTA can be used as a building block for the design of other biasing circuitry at low voltage such as bandgap references and voltage regulators." --
Author: Taoufik Bourdi
Publisher: Springer Science & Business Media
ISBN: 1402059280
Category : Technology & Engineering
Languages : en
Pages : 215
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Book Description
In this book, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. There is great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation. The developed techniques in the book can help in designing very low noise, high speed fractional-N frequency synthesizers.
Author: William F. Egan
Publisher: John Wiley & Sons
ISBN: 1118171152
Category : Technology & Engineering
Languages : en
Pages : 312
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Book Description
The latest frequency synthesis techniques, including sigma-delta,Diophantine, and all-digital Sigma-delta is a frequency synthesis technique that has risen inpopularity over the past decade due to its intensely digital natureand its ability to promote miniaturization. A continuation of thepopular Frequency Synthesis by Phase Lock, Second Edition, thistimely resource provides a broad introduction to sigma-delta bypairing practical simulation results with cutting-edge research.Advanced Frequency Synthesis by Phase Lock discusses bothsigma-delta and fractional-n—the still-in-use forerunner tosigma-delta—employing Simulink® models and detailedsimulations of results to promote a deeper understanding. After a brief introduction, the book shows how spurs areproduced at the synthesizer output by the basic process anddifferent methods for overcoming them. It investigates how variousdefects in sigma-delta synthesis contribute to spurs or noise inthe synthesized signal. Synthesizer configurations are analyzed,and it is revealed how to trade off the various noise sources bychoosing loop parameters. Other sigma-delta synthesis architecturesare then reviewed. The Simulink simulation models that provided data for thepreceding discussions are described, providing guidance in makinguse of such models for further exploration. Next, another methodfor achieving wide loop bandwidth simultaneously with fineresolution—the Diophantine Frequency Synthesizer—isintroduced. Operation at extreme bandwidths is also covered,further describing the analysis of synthesizers that push theirbandwidths close to the sampling-frequency limit. Lastly, the bookreviews a newly important technology that is poised to becomewidely used in high-production consumerelectronics—all-digital frequency synthesis. Detailed appendices provide in-depth discussion on variousstages of development, and many related resources are available fordownload, including Simulink models, MATLAB® scripts,spreadsheets, and executable programs. All these features make thisauthoritative reference ideal for electrical engineers who want toachieve an understanding of sigma-delta frequency synthesis and anawareness of the latest developments in the field.
Author: Howard Cam Luong
Publisher: Cambridge University Press
ISBN: 1139454579
Category : Technology & Engineering
Languages : en
Pages : 200
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Book Description
A frequency synthesizer is one of the most critical building blocks in any wireless transceiver system. Its design is getting more and more challenging as the demand for low-voltage low-power high-frequency wireless systems continuously grows. As the supply voltage is decreased, many existing design techniques are no longer applicable. This book provides the reader with architectures and design techniques to enable CMOS frequency synthesizers to operate at low supply voltage at high frequency with good phase noise and low power consumption. In addition to updating the reader on many of these techniques in depth, this book will also introduce useful guidelines and step-by-step procedure on behaviour simulations of frequency synthesizers. Finally, three successfully demonstrated CMOS synthesizer prototypes with detailed design consideration and description will be elaborated to illustrate potential applications of the architectures and design techniques described. For engineers, managers and researchers working in radio-frequency integrated-circuit design for wireless applications.
Author: George Gal
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Book Description
"High-frequency fractional-N PLLs in CMOS technology in the 30 to 40 GHz are very dicult to design when considering power, area, phase noise requirements and frequency range of operation. One of the diculties is to synthesize the loop lter of the PLL such that it meets the phase noise characteristics using the information available for all the components that make up the PLL. At the same time, predicting the phase noise output of the PLL using extracted layout results takes a long time to simulate and often the solution does not converge, thereby lengthening the design cycle. This thesis proposes a new methodology for designing high performance wide-band fractional-N PLLs in the 30-40 GHz range. The method begins by rst designing the phase-frequency detector/charge-pump, voltage-controlled oscillator and frequency divider circuit for realization in a specic CMOS technology. The method of choice mixes insight deemed from both a theoretical and simulation perspective. Next, the loop lter is derived based on the layout extracted behaviour of each component. Once complete, all components of the PLL are described using the high-level description language of Verilog-A available in the Cadence tool set over its full range of operating characteristics. Ideally, these components would be fabricated rst and characterized afterward. The Verilog-A description of the PLL enables a fast and ecient simulation of the complete PLL in a closed-loop conguration. This latter steps allows further optimization of the overall design. Two chips have been fabricated; one in a 0.13 m CMOS process from IBM and another in a 65 nm CMOS process from TSMC. One chip contain the design of a 28 GHz VCO and another containing the design of a programmable frequency divider circuit. Experimental results for both chip are provided." --
Author: Adem Aktas
Publisher:
ISBN:
Category : Frequency synthesizers
Languages : en
Pages :
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Book Description
Abstract: PLL (Phase-Locked Loop) frequency synthesizers are used in wireless transceivers for frequency conversion. Recent directions in PLL frequency synthesizer research and development are to fully integrate PLL synthesizers in CMOS technology, to improve phase noise performance, and to operate wide range of frequency bands and channel bandwidths. Fully integration of synthesizers in CMOS technology is desired for low cost, low power consumption and small size in mobile wireless terminals. Low phase noise is required by digital modulation techniques which have been used in new mobile standards for the efficient use of the frequency spectrum. Operation over a wide range of frequency bands and channel bandwidths are required to support migration and backward compatibility in the wireless standard evolution. This work investigates the PLL frequency synthesizer design and implementation in CMOS technology with focus on integration of wideband VCOs (Voltage-Controlled Oscillators). Phase noise of a PLL synthesizer is a major design parameter. A PLL noise model is developed for noise optimization purposes. Wideband RF VCO design with sub-bands is investigated. Frequency planning, synthesizer architecture and technology considerations are also explored for wideband VCO design. Band switching techniques VCO tuning range presented. Active VCO circuit topologies and resonator design are also presented. The PLL frequency synthesizers are designed and implemented for a multi-band/standard(IEEE 802.11a/b/g) WLAN radio in 0.18um CMOS. Phase noise trade-offs for PLL design are explored in this application. Development and design of a wideband VCO for this application is also presented. An auto calibration circuit is developed for VCO tuning band selection. Another application of the wideband PLL frequency synthesizer is designed and implemented for a fully integrated dual-mode frequency synthesizer for GSM and WCDMA standards in 0.5um CMOS. A hybrid integer-N/fractional-N architecture is developed to meet the multi-standard requirements. Design and implementation of high performance RF VCO depends on the RF models of the devices. RF CMOS characterization and modeling techniques are explored. Microwave wafer measurement and calibration techniques are also investigated for CMOS technology.
Author: Bram De Muer
Publisher: Springer Science & Business Media
ISBN: 0306480018
Category : Technology & Engineering
Languages : en
Pages : 270
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Book Description
CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
Author: Robert Bogdan Staszewski
Publisher: John Wiley & Sons
ISBN: 0470041943
Category : Technology & Engineering
Languages : en
Pages : 281
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Book Description
A new and innovative paradigm for RF frequency synthesis and wireless transmitter design Learn the techniques for designing and implementing an all-digital RF frequency synthesizer. In contrast to traditional RF techniques, this innovative book sets forth digitally intensive design techniques that lead the way to the development of low-cost, low-power, and highly integrated circuits for RF functions in deep submicron CMOS processes. Furthermore, the authors demonstrate how the architecture enables readers to integrate an RF front-end with the digital back-end onto a single silicon die using standard ASIC design flow. Taking a bottom-up approach that progressively builds skills and knowledge, the book begins with an introduction to basic concepts of frequency synthesis and then guides the reader through an all-digital RF frequency synthesizer design: Chapter 2 presents a digitally controlled oscillator (DCO), which is the foundation of a novel architecture, and introduces a time-domain model used for analysis and VHDL simulation Chapter 3 adds a hierarchical layer of arithmetic abstraction to the DCO that makes it easier to operate algorithmically Chapter 4 builds a phase correction mechanism around the DCO such that the system's frequency drift or wander performance matches that of the stable external frequency reference Chapter 5 presents an application of the all-digital RF synthesizer Chapter 6 describes the behavioral modeling and simulation methodology used in design The final chapter presents the implementation of a full transmitter and experimental results. The novel ideas presented here have been implemented and proven in two high-volume, commercial single-chip radios developed at Texas Instruments: Bluetooth and GSM. While the focus of the book is on RF frequency synthesizer design, the techniques can be applied to the design of other digitally assisted analog circuits as well. This book is a must-read for students and engineers who want to learn a new paradigm for RF frequency synthesis and wireless transmitter design using digitally intensive design techniques.
Author: Venceslav F. Kroupa
Publisher: John Wiley & Sons
ISBN: 9780470848661
Category : Technology & Engineering
Languages : en
Pages : 344
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Book Description
Phase lock loop frequency synthesis finds uses in a myriad of wireless applications - from local oscillators for receivers and transmitters to high performance RF test equipment. As the security and reliability of mobile communication transmissions have gained importance, PLL and frequency synthesisers have become increasingly topical subjects. Phase Lock Loops & Frequency Synthesis examines the various components that make up the phase lock loop design, including oscillators (crystal, voltage controlled), dividers and phase detectors. Interaction amongst the various components are also discussed. Real world problems such as power supply noise, shielding, grounding and isolation are given comprehensive coverage and solved examples with MATHCAD programs are presented throughout. * Presents a comprehesive study of phase lock loops and frequency synthesis in communication systems * Written by an internationally-recognised expert in the field * Details the problem of spurious signals in PLL frequency synthesizers, a topic neglected by available competing titles * Provides detailed theorectical background coupled with practical examples of state-of-the-art device design * MATHCAD programs and simulation software to accompany the design exercises and examples This combination of thorough theoretical treatment and guidance on practical applications will appeal to mobile communication circuit designers and advanced electrical engineering students.
Author: Bar-Giora Goldberg
Publisher: Elsevier
ISBN: 0080504299
Category : Technology & Engineering
Languages : en
Pages : 354
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Book Description
· In-depth coverage of modern digital implementations of frequency synthesis architectures· Numerous design examples drawn from actual engineering projectsDigital frequency synthesis is used in modern wireless and communications technologies such as radar, cellular telephony, satellite communications, electronic imaging, and spectroscopy. This is book is a comprehensive overview of digital frequency synthesis theory and applications, with a particular emphasis on the latest approaches using fractional-N phase-locked loop technology. In-depth coverage of modern digital implementations of frequency synthesis architectures Numerous design examples drawn from actual engineering projects
