Hierarchical Test Pattern Generation and Untestability Identification Techniques for Synchronous Sequential Circuits PDF Download
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Author: Anna Rannaste
Publisher:
ISBN: 9789949230419
Category :
Languages : en
Pages : 127
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Book Description
Author: Anna Rannaste
Publisher:
ISBN: 9789949230419
Category :
Languages : en
Pages : 127
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Book Description
Author: Heinrich Theodor Vierhaus
Publisher:
ISBN:
Category :
Languages : de
Pages : 19
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Book Description
Author: N. K. Jha
Publisher: Cambridge University Press
ISBN: 9781139437431
Category : Computers
Languages : en
Pages : 1022
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Book Description
Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through automatic test pattern generation, design for testability and built-in self-test of digital circuits before moving on to more advanced topics such as IDDQ testing, functional testing, delay fault testing, memory testing, and fault diagnosis. The book includes detailed treatment of the latest techniques including test generation for various fault models, discussion of testing techniques at different levels of integrated circuit hierarchy and a chapter on system-on-a-chip test synthesis. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Author: Robert Stewart Lewis
Publisher:
ISBN:
Category :
Languages : en
Pages :
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Author: Marinus Hendrik Konijnenburg
Publisher:
ISBN: 9789090120966
Category :
Languages : en
Pages : 226
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Author:
Publisher:
ISBN:
Category :
Languages : en
Pages : 0
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Book Description
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by developing results that permit dynamic, fully functional, collapsing of candidate faults. Fault collapsing permits the organization of faults into disjoint partitions based on the indistinguishability relation. These results are used to develop a diagnostic test pattern generation algorithm that has the same order of complexity as that of detection oriented test generation (ATPG). Techniques to identify untestable faults, based on exploiting indistinguishability identification, are also presented. Experimental results are presented on the ISCAS 89 benchmark circuits.
Author: Taavi Viilukas
Publisher:
ISBN: 9789949233847
Category :
Languages : en
Pages : 150
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Author: Carol Wawrukiewicz
Publisher:
ISBN:
Category :
Languages : en
Pages : 38
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Author: Venkat N. Koripalli
Publisher:
ISBN:
Category :
Languages : en
Pages : 74
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Book Description
The increase in speed and the shrinking of technology has led to modern day ICs becoming more sensitive to timing related defects. These defects must be rectified to prevent hazards in the circuit. The timing related defects can be identified with At-Speed Testing using the path delay fault model. A subset of the total number of paths known as critical paths cannot be sequentially activated i.e. we cannot find two successive vectors that activate a fault along the path. The elimination of untestable paths helps us to save a lot of time. In this report a new method, called the Launch-on-Shift is used to determine the testability of critical paths. The method uses a vector pair in which the first vector is the scan in steady state vector and the second vector is the function of the first vector.
Author: Bogdan Madzar
Publisher:
ISBN:
Category : Integrated circuits
Languages : en
Pages : 228
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Book Description
